SOI MOSFET with floating gate

Claim 2

A semiconductor device comprising a semiconductor substrate, a thin film single-crystalline semiconductor layer with an insulating layer interposed therebetween, the insulating layer containing a floating electroconductive layer buried therein, a MOSFET comprising source and drain regions in the thin film single-crystalline semiconductor layer, a gate insulating film on the thin film single-crystalline semiconductor layer, a polysilicon gate on the gate insulating film, a second thin film single-crystalline semiconductor layer on the insulating layer and insulated from the MOSFET, a tunnel insulating film on the second thin film single-crystalline semiconductor layer, a doped polysilicon layer on the tunnel insulating layer, a second metal electrode layer on the doped polysilicon layer, and a metal electrode layer connected to the semiconductor substrate acting as an electrode for applying a voltage to store electric charges in the floating electroconductive layer, the thin film single-crystalline semiconductor layer having a channel region at a portion corresponding to the polysilicon gate, the floating electroconductive layer being located at least at a position corresponding to the channel region of the MOSFET and being electrically insulated, wherein the second thin film single-crystalline semiconductor layer is connected to the floating electroconductive layer, whereby the electric charge is introduced in the floating electroconductive layer by applying a voltage between the metal electrode layer and the second metal electrode layer so that electrons are injected from the doped polysilicon layer into the floating electroconductive layer through the tunnel insulating film.

Claim 3

A semiconductor device according to claim 1 wherein the thin film single-crystalline semiconductor layer has a thickness smaller than a maximum width of a depletion layer of the channel region of the MOSFET.

Claim 4

A semiconductor device according to claim 1 wherein the floating electroconductive layer extends from an area corresponding to the source region to an area corresponding to the drain region in the insulating layer, a distance from the thin film single-crystalline semiconductor layer to the floating electroconductive layer being shorter in an area corresponding to the channel than in areas other than the area corresponding to the channel.

Claim 5

A semiconductor device comprising: a semiconductor substrate; a thin film single-crystalline semiconductor layer with a first insulating layer interposed therebetween; a plurality of MOSFETs comprising source and drain regions in the thin film single-crystalline semiconductor layer; a gate insulating film on the thin film single-crystalline semiconductor layer; a polysilicon gate on the gate insulating film; a floating electroconductive layer; and a metal electrode layer connected to the semiconductor substrate for applying such a voltage to store electric charges in the floating electroconductive layer, the thin film single-crystalline semiconductor layer having a channel region at a portion corresponding to the polysilicon gate, and the floating electroconductive layer being under the first insulating layer at least at a position corresponding to the channel region of one of the plurality of MOSFETs and a second insulating layer underlying the floating electroconductive layer, the floating electroconductive layer being by the first and second insulating layers and being electrically insulated wherein the floating electroconductive layer is common to more than one of the plurality of MOSFETs.

Claim 6

A semiconductor device comprising: a semiconductor substrate; a thin film single-crystalline semiconductor layer with a first insulating layer interposed therebetween; a plurality of MOSFETs comprising source and drain regions in the thin film single-crystalline semiconductor layer; a gate insulating film on the thin film single-crystalline semiconductor layer; a polysilicon gate on the gate insulating film; a floating electroconductive layer; and a metal electrode layer connected to the semiconductor substrate for applying such a voltage to store electric charges in the floating electroconductive layer, the thin film single-crystalline semiconductor layer having a channel region at a portion corresponding to the polysilicon gate, and the floating electroconductive layer being under the first insulating layer at least at a position corresponding to the channel region of one of the plurality of MOSFETs and a second insulating layer underlying the floating electroconductive layer, the floating electroconductive layer being by the first and second insulating layers and being electrically insulated wherein the floating electroconductive layer is common to more than one of the plurality of MOSFETs.

Claim 7

A semiconductor device according to claim 4 wherein the floating electroconductive layer has a portion where the thickness of the insulating layer between the floating electroconductive layer and the channel region in the single-crystalline layer of one of the MOSFETs is smaller than the thickness between the floating electroconductive layer and portions other the channel of the single-crystalline layer, so that said one of the MOSFETs is used to inject the electric charge into the floating electroconductive layer.

Claim 8

A semiconductor device according to claim 4 wherein the MOSFETs includes an N-channel MOSFET and a P-channel MOSFET.

Claim 9

A semiconductor device comprising: a semiconductor substrate, a thin film single-crystalline semiconductor layer with an insulating layer interposed therebetween, a plurality of MOSFETs each comprising source and drain regions in the thin film single-crystalline semiconductor layer, a gate insulating film on the thin film single-crystalline semiconductor layer, and a polysilicon gate on the gate insulating film, and an electrode, the thin film single-crystalline semiconductor layer having a channel region at a portion corresponding to the polysilicon gate, the insulating layer containing a floating electroconductive layer buried therein, the floating electroconductive layer being located at least at a position corresponding to the channel region of more than one said plurality of MOSFETs and being electrically insulated, and the electrode being connected to the semiconductor substrate for applying a voltage to store electric charges in the floating electroconductive layer.

Claim 10

A semiconductor device comprising: a semiconductor substrate, a thin film single-crystalline semiconductor layer with an insulating layer interposed therebetween, a plurality of MOSFETs each comprising source and drain regions in the thin film single-crystalline semiconductor layer, a gate insulating film on the thin film single-crystalline semiconductor layer, and a polysilicon gate on the gate insulating film, and an electrode, the thin film single-crystalline semiconductor layer having a channel region at a portion corresponding to the polysilicon gate, the insulating layer containing a floating electroconductive layer buried therein, the floating electroconductive layer being located at least at a position corresponding to the channel region of more than one said plurality of MOSFETs and being electrically insulated, and the electrode being connected to the semiconductor substrate for applying a voltage to store electric charges in the floating electroconductive layer.

Claim 11

A semiconductor device according to claim 7 wherein the floating electroconductive layer has a portion where the thickness of the insulating layer between the floating electroconductive layer and the channel region in the single-crystalline layer of one of the MOSFETs is smaller than the thickness between the floating electroconductive layer and portions of the single-crystalline layer other than said portion, so that said one of the MOSFETs is used to inject the electric charge into the floating electroconductive layer.

Claim 12

A semiconductor device according to claim 7 wherein the MOSFETs includes an N-channel MOSFET and a P-channel MOSFET.

Claim 13

A semiconductor device comprising: a semiconductor substrate; a thin film single-crystalline semiconductor layer with a first insulating layer interposed therebetween; a MOSFET comprising source and drain regions in the thin film single-crystalline semiconductor layer; a gate insulating film on the thin film single-crystalline semiconductor layer; a polysilicon gate on the gate insulating film; a floating electroconductive layer; a metal electrode layer connected to the semiconductor substrate for applying such a voltage to store electric charges in the floating electroconductive layer; a second thin film single-crystalline semiconductor layer on the first insulating layer; a tunnel insulating film on the second thin film single-crystalline semiconductor layer; a doped polysilicon layer on the tunnel insulating layer and a second metal electrode layer on the doped polysilicon layer, the thin film single-crystalline semiconductor layer having a channel region at a portion corresponding to the polysilicon gate, and the floating electroconductive layer being under the first insulating layer at least at a position corresponding to the channel region of the MOSFET and a second insulating layer underlying the floating electroconductive layer, the floating electroconductive layer being buried by the first and second insulating layers and being electrically insulated, the second thin film single-crystalline semiconductor layer being insulated from the MOSFET and connected to the floating electroconductive layer, by which the electric charge is introduced in the floating electroconductive layer by applying a voltage between the metal electrode layer and the second metal layer so that the electric charge is injected from the doped polysilicon layer into the floating electroconductive layer through the tunnel insulating film.

Claim 14

A semiconductor device comprising: a semiconductor substrate; a thin film single-crystalline semiconductor layer with a first insulating layer interposed therebetween; a MOSFET comprising source and drain regions in the thin film single-crystalline semiconductor layer; a gate insulating film on the thin film single-crystalline semiconductor layer; a polysilicon gate on the gate insulating film; a floating electroconductive layer; a metal electrode layer connected to the semiconductor substrate for applying such a voltage to store electric charges in the floating electroconductive layer; a second thin film single-crystalline semiconductor layer on the first insulating layer; a tunnel insulating film on the second thin film single-crystalline semiconductor layer; a doped polysilicon layer on the tunnel insulating layer and a second metal electrode layer on the doped polysilicon layer, the thin film single-crystalline semiconductor layer having a channel region at a portion corresponding to the polysilicon gate, and the floating electroconductive layer being under the first insulating layer at least at a position corresponding to the channel region of the MOSFET and a second insulating layer underlying the floating electroconductive layer, the floating electroconductive layer being buried by the first and second insulating layers and being electrically insulated, the second thin film single-crystalline semiconductor layer being insulated from the MOSFET and connected to the floating electroconductive layer, by which the electric charge is introduced in the floating electroconductive layer by applying a voltage between the metal electrode layer and the second metal layer so that the electric charge is injected from the doped polysilicon layer into the floating electroconductive layer through the tunnel insulating film.