Semiconductor memory device and defective memory cell repair circuit

Claim 1

A semiconductor memory device comprising: a plurality of memory blocks, each of said memory blocks having an array of memory cells provided thereon arranged in a matrix of rows and columns of individual memory cells each array of memory cells including a main array sector of rows and columns of memory cells as part of a regular memory configuration, at least some of the arrays of memory cells including a redundant group of a plurality of one of the rows and columns of memory cells as redundant memory; a plurality of redundant group selection lines corresponding in number to the plurality of said one of the rows and columns of memory cells included in each of said redundant groups; the plurality of said one of the rows and columns of memory cells included in each of said redundant groups having a first redundant address of a portion only of the number of address bits to be provided on an address signal line for addressing memory cells of the regular memory configuration; a first plurality of programmable fuses respectively connected to an address signal line; a redundant memory address group decoder for selecting one redundant group of a plurality of said one of the rows and columns of memory cells in response to the first redundant address defined by said portion of the address bits provided on the address signal line; a second plurality of programmable fuses respectively connected to the address signal line; and a redundant memory address decoder for selecting a portion of a selected one redundant group in response to a second redundant address having a number of address bits constituting all of the address bits as provided on the address signal line to define the address of a memory cell.