Patent US5487035A successfully refreshed from Google Patents.
US5487035A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of multiplexed data reading/writing suitable for video-on-demand system
Assignee: NTT Inc
•
Filing: 1994-08-26
•
Granted: 1996-01-23
•
Expires: 2014-08-26
Abstract
Abstract A method of multiplexed data reading/writing capable of admitting more than n requests simultaneously in a configuration in which m sets of n-fold multiplexed sub-systems are provided in parallel. Each data is divided into a plurality of segment data which are stored in a prescribed order among the memory devices, and m memory control units are connected with m×n input/output channels selectively and sequentially in units of time-slots such that each memory control unit is connected with each of input/output channel at least once within a prescribed period. Then, the reading/writing operations of the segment data stored in the memory devices are carried out by making accesses from m memory control units in parallel at each time-slot such that each segment data read/written by each memory control unit from/into one of the memory devices connected thereto at each time-slot is transmitted to/from one of m×n input/output channels connected thereto at each time-slot.
Inventors
- 👤 Kazutoshi Nishimura
- 👤 Hideki Sakamoto
- 👤 Hideharu Suzuki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 18:35
CPC Classifications
H; H04; H04N; H04N7/00; H04N7/16; H04N7/173; H04N7/17309; H04N7/17336
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
205 words
A method of multiplexed data reading/writing with respect to a plurality of memory devices through m memory control means connected to the memory devices and m×n input/output channels selectively connected to said m memory control means via switching means, where m and n are integers greater than one, the method comprising the steps of: (a) dividing each data into a plurality of segment data and storing the segment data of each data in a prescribed order among the memory devices; (b) connecting said m memory control means with said m×n input/output channels selectively and sequentially by the switching means in units of time-slots such that each of said m memory control means is connected with each of said m×n input/output channels at least once within a prescribed period; and (c) carrying out the reading/writing operations of the segment data stored by the step (a) in the memory devices by making accesses from said m memory control means in parallel at each time-slot such that each segment data read/written by each of said m memory control means from/into one of the memory devices connected thereto at each time-slot is transmitted to/from one of said m×n input/output channels connected by the step (b) thereto at each time-slot.
Claim 2
Independent Claim
205 words
A method of multiplexed data reading/writing with respect to a plurality of memory devices through m memory control means connected to the memory devices and m×n input/output channels selectively connected to said m memory control means via switching means, where m and n are integers greater than one, the method comprising the steps of: (a) dividing each data into a plurality of segment data and storing the segment data of each data in a prescribed order among the memory devices; (b) connecting said m memory control means with said m×n input/output channels selectively and sequentially by the switching means in units of time-slots such that each of said m memory control means is connected with each of said m×n input/output channels at least once within a prescribed period; and (c) carrying out the reading/writing operations of the segment data stored by the step (a) in the memory devices by making accesses from said m memory control means in parallel at each time-slot such that each segment data read/written by each of said m memory control means from/into one of the memory devices connected thereto at each time-slot is transmitted to/from one of said m×n input/output channels connected by the step (b) thereto at each time-slot.
Claim 3
Dependent Claim
30 words
The method of claim 1, wherein at the step (a), the prescribed order to store the segment data in the memory devices is a cyclic order among the memory devices.
Claim 4
Dependent Claim
99 words
The method of claim 1, wherein at the step (b), the prescribed period is defined by m×n×h time-slots divided into m small periods, each small period being defined by n×h time-slots, where h is a natural number, and said m memory control means are connected with said m×n input/output channels selectively and sequentially such that an l-th memory control means is connected with [(j+l mod m).n+i]-th input/output channels for h times in a j-th small period, where l is an integer for which 0≦l≦m-1, j is an integer for which 0≦j≦m-1, and i is an integer for which 1≦i≦n.
Claim 5
Dependent Claim
29 words
The method of claim 1, wherein at the step (c), the reading/writing operations through said m memory control means and said m×n input/output channels are synchronized at each time-slot.
Claim 6
Dependent Claim
30 words
The method of claim 1, wherein at the step (c), the reading/writing operations through said m memory control means and said m×n input/output channels are synchronized at each n time-slots.
Claim 7
Dependent Claim
40 words
The method of claim 1, wherein at the step (c), the reading/writing operations through said m memory control means and said m×n input/output channels are synchronized at each small period defined by n×h time-slots, where h is a natural number.
Claim 8
Dependent Claim
40 words
The method of claim 1, wherein at the step (c), the reading/writing operations through said m memory control means and said m×n input/output channels are synchronized at each large period defined by m×n×h time-slots, where h is a natural number.
Claim 9
Dependent Claim
58 words
The method of claim 1, wherein said m×n input/output channels are connected with a plurality of terminals via a network, and at the step (b), the switching means are controlled to connect said m memory control means with said m×n input/output channels selectively and sequentially in accordance with requests for reading/writing of each data issued by the terminals.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-01-22 | 1999-07-24 | 2000-01-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-01-22 | 2003-07-24 | 2004-01-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-01-22 | 2007-07-24 | 2008-01-23 | $7700.00 | Window Closed / Lapsed |