Patent US5487022A successfully refreshed from Google Patents.
US5487022A
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Normalization method for floating point numbers
Assignee: Texas Instruments Inc
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Filing: 1994-03-08
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Granted: 1996-01-23
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Expires: 2014-03-08
Abstract
Abstract A floating point normalization circuit and method decodes the exponent generating a coded multibit output corresponding to the maximum decrease in the exponent within the minimum expressible exponent. This coded multibit output is bit-wise ORed with the mantissa. A left most one circuit detects the bit position of the most significant bit of the logical OR output having a "1". The mantissa and exponent are them normalized according to this number. The mantissa is left shifted an amount equal to this detected bit position of a most significant bit having a "1". The exponent is decremented an amount equal to this detected bit position of a most significant bit having a "1". The exponent decoder generates said coded multibit output in the form of a mantissa equal to the minimum mantissa that can be normalized for the input exponent part of the floating point number. This minimum mantissa is equal to 2.sup.(M+N), where M is the minimum expressible exponent and N is the exponent. In the preferred embodiment, the exponent decoder includes a two to four line decoder for each pair of bits of the exponent part of the floating point number, and an AND gate connected to selected outputs of said two to four line decoders for each bit of said mantissa.
Inventors
- 👤 Richard Simpson
- 👤 Erick D. Oakland
- 👤 Graham M. Barr
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 16:49
CPC Classifications
G; G06; G06F; G06F5/00; G06F5/01; G06F5/012
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
280 words
A floating point normalization circuit receiving a mantissa part and an exponent part of a floating point number, the exponent part having a minimum expressible exponent, said circuit comprising: an exponent decoder receiving the exponent part of the floating point number and generating a coded multibit output corresponding to a maximum decrease in the exponent part of the floating point number within the minimum expressible exponent, said exponent decoder including a two to four line decoder for each pair of bits of the exponent part of the floating point number, and an AND gate connected to selected outputs of said two to four line decoders for each bit of said mantissa; a bit-wise OR circuit connected to said exponent decoder, receiving the mantissa part of the floating point number and said coded multibit output and forming a logical OR output of each bit of the mantissa part with a corresponding bit of said coded multibit output; a left most one circuit connected to said bit-wise OR circuit detecting a bit position of a most significant bit of said logical OR output having a "1"; a left shifter circuit connected to said left most one circuit and receiving the mantissa part of the floating point number, said left shifter left shifting the mantissa part the floating point number an amount equal to said detected bit position of a most significant bit having a "1"; and a decrementer connected to said left most one circuit and receiving the exponent part of the floating point number, said decrementer decrementing the exponent part of the floating point number an amount equal to said detected bit position of a most significant bit having a "1".
Claim 2
Dependent Claim
280 words
A floating point normalization circuit receiving a mantissa part and an exponent part of a floating point number, the exponent part having a minimum expressible exponent, said circuit comprising: an exponent decoder receiving the exponent part of the floating point number and generating a coded multibit output corresponding to a maximum decrease in the exponent part of the floating point number within the minimum expressible exponent, said exponent decoder including a two to four line decoder for each pair of bits of the exponent part of the floating point number, and an AND gate connected to selected outputs of said two to four line decoders for each bit of said mantissa; a bit-wise OR circuit connected to said exponent decoder, receiving the mantissa part of the floating point number and said coded multibit output and forming a logical OR output of each bit of the mantissa part with a corresponding bit of said coded multibit output; a left most one circuit connected to said bit-wise OR circuit detecting a bit position of a most significant bit of said logical OR output having a "1"; a left shifter circuit connected to said left most one circuit and receiving the mantissa part of the floating point number, said left shifter left shifting the mantissa part the floating point number an amount equal to said detected bit position of a most significant bit having a "1"; and a decrementer connected to said left most one circuit and receiving the exponent part of the floating point number, said decrementer decrementing the exponent part of the floating point number an amount equal to said detected bit position of a most significant bit having a "1".
Claim 3
Dependent Claim
48 words
The floating point normalization circuit of claim 1, wherein: said exponent decoder generates said coded multibit output in the form of a mantissa equal to the minimum mantissa part of a floating point number that can be normalized for the input exponent part of the floating point number.
Claim 4
Dependent Claim
71 words
The floating point normalization circuit of claim 2, wherein: said exponent decoder generates said coded multibit output equal to 2.sup.(M-N) if M-N is less than the number of bits of the mantissa part, where M is said minimum expressible exponent and N is the exponent part of the floating point number, and equal to zero if M-N is greater than or equal to the number of bits of the mantissa part.
Claim 5
Dependent Claim
169 words
A floating point normalization method for a floating point number having a mantissa and an exponent, the exponent having a minimum expressible exponent, said method comprising the steps of: generating a coded multibit output corresponding to a maximum decrease in the exponent part of the floating point number within the minimum expressible exponent, said step of generating said coded multibit output including generating a four line output for each pair of bits of the exponent, and forming the logical AND of selected four line outputs for each bit of said mantissa; forming a bit-wise logical OR output of each bit of the mantissa with a corresponding bit of said coded multibit output; detecting a bit position of a most significant bit of said logical OR output having a "1"; left shifting the mantissa an amount equal to said detected bit position of a most significant bit having a "1"; and decrementing the exponent an amount equal to said detected bit position of a most significant bit having a "1".
Claim 6
Dependent Claim
169 words
A floating point normalization method for a floating point number having a mantissa and an exponent, the exponent having a minimum expressible exponent, said method comprising the steps of: generating a coded multibit output corresponding to a maximum decrease in the exponent part of the floating point number within the minimum expressible exponent, said step of generating said coded multibit output including generating a four line output for each pair of bits of the exponent, and forming the logical AND of selected four line outputs for each bit of said mantissa; forming a bit-wise logical OR output of each bit of the mantissa with a corresponding bit of said coded multibit output; detecting a bit position of a most significant bit of said logical OR output having a "1"; left shifting the mantissa an amount equal to said detected bit position of a most significant bit having a "1"; and decrementing the exponent an amount equal to said detected bit position of a most significant bit having a "1".
Claim 7
Dependent Claim
34 words
The floating point normalization method of claim 4, wherein: said step of generating said coded multibit output forms said coded multibit output equal to the minimum mantissa that can be normalized for the exponent.
Claim 8
Dependent Claim
68 words
The floating point normalization method of claim 5, wherein: said step of generating said coded multibit output forms a mantissa equal to 2.sup.(M-N) if M-N is less than the number of bits of the mantissa part, where M is said minimum expressible exponent and N is the exponent, and equal to zero if M-N is greater than or equal to the number of bits of the mantissa part.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-01-22 | 1999-07-24 | 2000-01-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-01-22 | 2003-07-24 | 2004-01-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-01-22 | 2007-07-24 | 2008-01-23 | $7700.00 | Window Closed / Lapsed |