Patent US5486868A successfully refreshed from Google Patents.
US5486868A
Expired / Lapsed
US
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Generator for scan timing of multiple industrial standards
Assignee: Winbond Electronics Corp
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Filing: 1995-05-19
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Granted: 1996-01-23
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Expires: 2015-05-19
Abstract
Abstract The invention inputs a single timing clock. Through procedure of mode setting, the invention generates the required timings corresponding to the display mode selected. In the invention, a programmable mode register, a mode decoder, a pixel timing generator, a horizontal timing generator, a vertical timing generator, a composite timing generator, AND gate, EXCLUSIVE NOR gate, and a selector are provided. The invention may generate the required timings for NTSC interlace mode, NTSC non-interlace mode, PAL interlace mode, PAL non-interlace mode, VGA 60 Hz progressive mode and VGA 50 Hz progressive mode.
Inventors
- 👤 Rong-Fuh Shyu
- 👤 Wen-I Chu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 22:25
CPC Classifications
H; H04; H04N; H04N5/00; H04N5/44; H04N5/46; H04N5/04; H04N5/06
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
286 words
A video scan timing generator, the video scan timing generator inputting a single timing clock, comprising: a programmable mode register for storing and outputing a mode value which corresponds to a predetermined mode operation; a mode decoder, adapted to receive the mode value, for outputing a mode control signal; a first timing generator, adapted to receive the mode control signal and the single timing clock, for generating a pixel clock corresponding to the predetermined mode operation; a second timing generator, adapted to receive the pixel clock and the mode control signal, for generating a horizontal synchronization signal and a horizontal blanking signal corresponding to the predetermined mode operation, the second timing generator including a first counter outputing a pixel -- count value; a third timing generator, adapted to receive the pixel clock, the pixel -- count value and the mode control signal, for generating a vertical synchronization signal, a vertical blanking signal and a top -- field signal corresponding to the predetermined mode operation, the third timing generator including a second counter outputing a horizontal -- count value; a fourth timing generator, adapted to receive the pixel clock, the pixel -- count value, the horizontal -- count value, the horizontal synchronization signal, the vertical synchronization signal and the mode control signal, for selectively generating an interlace composite synchronization signal; AND gate, adapted to receive the horizontal and the vertical blanking signal, for generating a composite blanking signal; EXCLUSIVE NOR gate, adapted to perform EXCLUSIVE NOR operation to the horizontal synchronization signal and the vertical synchronization signal, for generating a non-interlaced composite synchronization signal; a selector, in response to the mode control signal, for selectively outputing the non-interlace composite synchronization signal and the interlace composite synchronization signal.
Claim 2
Dependent Claim
286 words
A video scan timing generator, the video scan timing generator inputting a single timing clock, comprising: a programmable mode register for storing and outputing a mode value which corresponds to a predetermined mode operation; a mode decoder, adapted to receive the mode value, for outputing a mode control signal; a first timing generator, adapted to receive the mode control signal and the single timing clock, for generating a pixel clock corresponding to the predetermined mode operation; a second timing generator, adapted to receive the pixel clock and the mode control signal, for generating a horizontal synchronization signal and a horizontal blanking signal corresponding to the predetermined mode operation, the second timing generator including a first counter outputing a pixel -- count value; a third timing generator, adapted to receive the pixel clock, the pixel -- count value and the mode control signal, for generating a vertical synchronization signal, a vertical blanking signal and a top -- field signal corresponding to the predetermined mode operation, the third timing generator including a second counter outputing a horizontal -- count value; a fourth timing generator, adapted to receive the pixel clock, the pixel -- count value, the horizontal -- count value, the horizontal synchronization signal, the vertical synchronization signal and the mode control signal, for selectively generating an interlace composite synchronization signal; AND gate, adapted to receive the horizontal and the vertical blanking signal, for generating a composite blanking signal; EXCLUSIVE NOR gate, adapted to perform EXCLUSIVE NOR operation to the horizontal synchronization signal and the vertical synchronization signal, for generating a non-interlaced composite synchronization signal; a selector, in response to the mode control signal, for selectively outputing the non-interlace composite synchronization signal and the interlace composite synchronization signal.
Claim 3
Dependent Claim
28 words
The timing generator as recited in claim 1, wherein the mode register comprises a first bit discriminating a TV scan operation from a personal computer VGA scan operation.
Claim 4
Dependent Claim
39 words
The timing generator as recited in claim 2, wherein the mode register comprises a second bit, and as the first bit indicates the TV scan operation, the second bit discriminates a NTSC scan operation from a PAL scan operation.
Claim 5
Dependent Claim
44 words
The timing generator as recited in claim 2, wherein the mode register comprises a second bit, as the first bit indicates the personal computer VGA scan operation, the second bit discriminates a 60 Hz vertical refresh operation from a 50 Hz vertical refresh operation.
Claim 6
Dependent Claim
39 words
The timing generator as recited in claim 2, wherein the mode register comprises a third bit, and as the first bit indicates the TV scan operation, the third bit discriminates an interlace scan operation from a non-interlace scan operation.
Claim 7
Dependent Claim
33 words
The timing generator as recited in claim 2, wherein the mode register comprises a third bit, as the first bit indicates the personal computer VGA scan operation, the third bit represents don't care.
Claim 8
Dependent Claim
18 words
The timing generator as recited in claim 1, wherein the single timing clock has frequency of 40.5 MHz.
Claim 9
Dependent Claim
27 words
The timing generator as recited in claim 1, as the predetermined mode operation is a TV scan operation, the generated pixel clock has frequency of 13.5 MHz.
Claim 10
Dependent Claim
29 words
The timing generator as recited in claim 1, as the predetermined mode operation is a personal computer VGA scan operation, the generated pixel clock has frequency of 27 MHz.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-01-22 | 1999-07-24 | 2000-01-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-01-22 | 2003-07-24 | 2004-01-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-01-22 | 2007-07-24 | 2008-01-23 | $7700.00 | Window Closed / Lapsed |