Low power differential receiver input circuit

Claim 2

A low power differential receiver input circuit for converting first and second differential input signals respectively having first and second voltage levels into first and second differential output siqnals respectively having third and fourth voltage levels, the receiver circuit comprising: first and second input terminals for respectively receiving the first and second differential input signals; first and second output terminals for respectively transmitting the first and second differential output signals; a first resistor connected between the first input terminal and the first output terminal; a second resistor connected between the second input terminal and the second output terminal; a first p-channel MOSFET having a drain connected to the first output terminal; a first n-channel MOSFET having a drain connected to the first output terminal; a second p-channel MOSFET having a drain connected to the second output terminal; and a second n-channel MOSFET having a drain connected to the second output terminal; wherein the first input terminal is connected to a gate of the second p-channel MOSFET and to a gate of the second n-channel MOSFET such that the first voltage level controls conductivities of the second p-channel MOSFET and the second n-channel MOSFET thereby producing the second differential output signal at the second output terminal; and wherein the second input terminal is connected to a gate of the first p-channel MOSFET and to a gate of the first n-channel MOSFET such that the second voltage of the second differential input signal controls the first p-channel MOSFET and the first n-channel MOSFET thereby producing the first differential output signal at the first output terminal.

Claim 3

An low power differential receiver circuit of claim 1, wherein: the drain of the first p-channel transistor is connected to the first output terminal through a third resistor; the drain of the first n-channel transistor is connected to the first output terminal through a fourth resistor; the drain of the second p-channel transistor is connected to the second output terminal through a fifth resistor; and the drain of the second n-channel transistor is connected to the second output terminal through a sixth resistor.

Claim 4

A low power differential receiver circuit for respectively converting first and second differential input signals into first and second differential output signals, the receiver circuit comprising: first and second input terminals for respectively receiving the first and second differential input signals, the first and second input terminals being respectively connected to first and second nodes; a first output terminal connected to the first node through a first resistor; a second output terminal connected to the second node through a second resistor; a first transistor of a first type having a gate connected to the second node, a source connected to a first voltage source and a drain connected to the first output terminal; a second transistor of a second type having a gate connected to the second node, a drain connected to the first output terminal and a source connected to a second voltage source; a third transistor of the first type having a gate connected directly to the first node, a source connected to the first voltage source and a drain connected to the second output terminal; and a fourth transistor of the second type having a gate connected directly to the first node, a drain connected to the second output terminal and a source connected to the second voltage source; wherein a voltage of the first differential input signal controls the third transistor of the first type and the fourth transistor of the second type, thereby producing the second differential output signal at the second output terminal; and wherein a voltage of the second differential input signal controls the first transistor of the first type and the second transistor of the second type thereby producing the first differential output signal at the first output terminal.

Claim 5

A low power differential receiver circuit for respectively converting first and second differential input signals into first and second differential output signals, the receiver circuit comprising: first and second input terminals for respectively receiving the first and second differential input signals, the first and second input terminals being respectively connected to first and second nodes; a first output terminal connected to the first node through a first resistor; a second output terminal connected to the second node through a second resistor; a first transistor of a first type having a gate connected to the second node, a source connected to a first voltage source and a drain connected to the first output terminal; a second transistor of a second type having a gate connected to the second node, a drain connected to the first output terminal and a source connected to a second voltage source; a third transistor of the first type having a gate connected directly to the first node, a source connected to the first voltage source and a drain connected to the second output terminal; and a fourth transistor of the second type having a gate connected directly to the first node, a drain connected to the second output terminal and a source connected to the second voltage source; wherein a voltage of the first differential input signal controls the third transistor of the first type and the fourth transistor of the second type, thereby producing the second differential output signal at the second output terminal; and wherein a voltage of the second differential input signal controls the first transistor of the first type and the second transistor of the second type thereby producing the first differential output signal at the first output terminal.

Claim 6

An low power differential receiver circuit of claim 3, further comprising a third resistor connected between the first and second input terminals.

Claim 7

An low power differential receiver circuit of claim 4, wherein the first input terminal is connected to a first voltage source, and the second input terminal is connected to a second voltage.

Claim 8

An low power differential receiver circuit of claim 5, wherein: the drain of the first transistor is connected to the first output terminal through a fourth resistor; the drain of the second transistor is connected to the first output terminal through a fifth resistor; the drain of the third transistor is connected to the second output terminal through a sixth resistor; and the drain of the fourth transistor is connected to the second output terminal through a seventh resistor.

Claim 9

An low power differential receiver circuit of claim 6 further comprising: an eighth resistor connected between the first node and the first input terminal; and a ninth resistor connected between the second node and the second input terminal.

Claim 10

An low power differential receiver circuit of claim 7 further comprising: a first capacitor connected in parallel with the first resistor; and a second capacitor connected in parallel with the second resistor.

Claim 11

An low power differential receiver circuit of claim 8 further comprising: a tenth resistor connected between the first voltage source and the first input terminal; and an eleventh resistor connected between the second voltage source and the second input terminal.

Claim 14

The method of claim 10 further comprising: biasing the first differential signal by connecting the first input terminal to the first voltage source through a first resistor; and biasing the second differential signal by connecting the second input terminal to the second voltage source through a second resistor.

Claim 15

The method of claim 11 further comprising: connecting third resistor between the first and second input terminals.