Microprocessor wherein the number of register output signal liner connected to the buses are reduced reducing the load capacity of the buses

Claim 1

A microprocessor comprising: a plurality of dynamic buses each chargeable and dischargeable to have data established thereon; a precharge circuit for precharging the plurality of buses in response to a first clock signal a plurality of first switches connected to a common electrode having a ground level, each of said first switches being operable to open and close in response to one of a plurality of first operation signals inputted thereto; a plurality of second switches each of which is connected between a respective one of the plurality of buses and a respective one of the first switches and is operable to open and close in response to one of a plurality of second operation signals inputted thereto; a first signal generating means for generating said plurality of second operation signals and selectively outputting the same to the second switches in synchronism with a second clock signal; a plurality of wiring electrodes; a plurality of registers each of which is connected at an input side thereof to a respective one of said plurality of buses for latching data therefrom in response to one of a plurality of first select signals inputted to said register and is connected at an output side thereof to a respective one of said plurality of wiring electrodes for clocking out thereon the latched data in response to a third clock signal; a second signal generating means for generating said plurality of first select signals and selectively outputting the same to the plurality of registers in synchronism with the second clock signal; a plurality of selectors each of which is connected at an input side thereof to a respective one of said plurality of wiring electrodes for receiving therefrom said clocked out data in response to one of a plurality of second select signals inputted to the selector and is connected at an output side thereof to a respective one of the plurality of first switches for outputting thereto the received data as said one of said plurality of first operation signals; a third signal generating means for generating said plurality of second select signals and selectively outputting the same to said plurality of selectors in response to said third clock signal; and a control means for controlling said first, second and third signal generating means in synchronism with said first clock signal.