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US5485467A
Expired / Lapsed
US
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Versatile reconfigurable matrix based built-in self-test processor for minimizing fault grading
Assignee: NXP BV
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Filing: 1993-09-24
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Granted: 1996-01-16
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Expires: 2013-09-24
Abstract
Abstract A built-in self-test circuitry includes a design under test and a self-test processor. Included within the design under test is a plurality of scan row registers. The self-test processor includes a command processing section and a signal generating section. The command processing section receives information which indicates the configuration of the scan row registers. The signal generating section generates control signals which control the built-in self-testing of the circuit. The control signals are based on the information received by the command processing section. In the preferred embodiment, the command processing section includes a shift section, a load section, and a signature section. The shift section receives information which indicates a number of bits in each scan row register. The load section receives information which indicates a number of loads into the scan row registers. The signature section receives information which indicates a bit length of signature registers used to generate a checksum. The signature section additionally receives information which indicates a number of scan row registers.
Inventors
- 👤 Habibollah Golnabi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 10:41
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318505
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
122 words
A method for controlling built-in self-testing of a circuit in which during self-testing scan row registers within the circuit provide input to combination logic and output from the combination logic is utilized to generate a checksum, the method comprising the steps of: (a) receiving, by a self-test processor within the circuit, configuration information which indicates the configuration of the scan row registers, the configuration information including information which indicates a number of bits in each scan row register; and, (b) generating, by the self-test processor, control signals which control the built-in self-testing of the circuit, the control signals including signals which control data transfer to the scan row register, the control signals being based on the configuration information received in step (a).
Claim 2
Independent Claim
122 words
A method for controlling built-in self-testing of a circuit in which during self-testing scan row registers within the circuit provide input to combination logic and output from the combination logic is utilized to generate a checksum, the method comprising the steps of: (a) receiving, by a self-test processor within the circuit, configuration information which indicates the configuration of the scan row registers, the configuration information including information which indicates a number of bits in each scan row register; and, (b) generating, by the self-test processor, control signals which control the built-in self-testing of the circuit, the control signals including signals which control data transfer to the scan row register, the control signals being based on the configuration information received in step (a).
Claim 3
Dependent Claim
31 words
A method as in claim 1 wherein step (a) includes the following substep: (a.1) receiving, by the self-test processor within the circuit, information which indicates a number of scan row registers.
Claim 4
Dependent Claim
37 words
A method as in claim 2 wherein step (a) additionally includes the substep of: (a.2) receiving, by the self-test processor within the circuit, information which indicates a bit length of signature registers used to generate a checksum.
Claim 5
Dependent Claim
35 words
A method as in claim 3 wherein step (a) additionally includes the substep of: (a.3) receiving, by the self-test processor within the circuit, information which indicates a number of loads into the scan row registers.
Claim 6
Dependent Claim
106 words
Built-in self-test circuitry within an integrated circuit, the built-in self-test circuitry comprising: a design under test including a plurality of scan row registers; and, a self-test processor, coupled to the design under test, the self-test processor including: command processing means for receiving configuration information which indicates the configuration of the scan row registers, the configuration information including information which indicates a number of bits in each scan row register, and signal generating means, coupled to the command processing means, for generating control signals which control the built-in self-testing of the circuit, the control signals being based on the configuration information received by the command processing means.
Claim 7
Dependent Claim
106 words
Built-in self-test circuitry within an integrated circuit, the built-in self-test circuitry comprising: a design under test including a plurality of scan row registers; and, a self-test processor, coupled to the design under test, the self-test processor including: command processing means for receiving configuration information which indicates the configuration of the scan row registers, the configuration information including information which indicates a number of bits in each scan row register, and signal generating means, coupled to the command processing means, for generating control signals which control the built-in self-testing of the circuit, the control signals being based on the configuration information received by the command processing means.
Claim 8
Dependent Claim
30 words
Built-in self-test circuitry as in claim 5 wherein the command processing means includes: shift means for receiving the information which indicates the number of bits in each scan row register.
Claim 9
Dependent Claim
30 words
Built-in self-test circuitry as in claim 6 wherein the command processing means additionally includes: load means for receiving information which indicates a number of loads into the scan row registers.
Claim 10
Dependent Claim
44 words
Built-in self-test circuitry as in claim 7 wherein the command processing means additionally includes: signature means for receiving information which indicates a bit length of signature registers used to generate a checksum and for receiving information which indicates a number of scan row registers.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-01-15 | 1999-07-17 | 2000-01-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-01-15 | 2003-07-17 | 2004-01-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-01-15 | 2007-07-17 | 2008-01-16 | $7700.00 | Window Closed / Lapsed |