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US5485138A Expired / Lapsed US ⏱️ 0.0 years remaining

Thin film resistor and method for manufacturing the same

Assignee: Texas Instruments Inc
•
Filing: 1994-06-09
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Granted: 1996-01-16
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Expires: 2014-06-09
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Abstract

Abstract An inverted thin film resistor structure comprises a metallic interconnect layer having predetermined patterns delineating two or more metallic interconnect leads (e.g. Al 36) overlaying a supporting layer (e.g. SiO2 32), an interlevel dielectric layer (e.g. SiO2 40) overlaying the supporting layer, and planarized so as to expose a top contact portion of the metallic interconnect leads, and an inverted thin film resistor (e.g. TaN 44) overlaying a portion of the planarized interlevel dielectric layer and overlaying the exposed top contact portions of the metallic interconnect leads. The novel inverted thin film resistor structure does not require a protective metal layer and does not require any vias in direct contact with the resistor. In addition, both the thin film resistor and the metallic interconnect can be formed with pattern and etch techniques.

Inventors

  • 👤 Frank J. Morris

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-09 11:20
CPC Classifications
H; H10; H10D; H10D1/00; H10D1/40; H10D1/47; H10D1/474; H01; H01C; H01C1/00; H01C1/14

Claims Analysis

Total Claims: 19
Claim 1
Independent Claim 94 words
A method of fabricating a microelectronic inverted thin film resistor structure, said method comprising: (a) forming a metallic interconnect layer having predetermined patterns delineating two or more metallic interconnect leads, on a supporting layer; (b) forming an interlevel dielectric layer on said metallic interconnect layer and said supporting layer; (c) planarizing said interlevel dielectric layer so as to expose a top contact portion of said metallic interconnect leads; and (d) forming an inverted thin film resistor on said planarized interlevel dielectric layer and on said exposed top contact portion of said metallic interconnect leads.
Claim 2
Independent Claim 94 words
A method of fabricating a microelectronic inverted thin film resistor structure, said method comprising: (a) forming a metallic interconnect layer having predetermined patterns delineating two or more metallic interconnect leads, on a supporting layer; (b) forming an interlevel dielectric layer on said metallic interconnect layer and said supporting layer; (c) planarizing said interlevel dielectric layer so as to expose a top contact portion of said metallic interconnect leads; and (d) forming an inverted thin film resistor on said planarized interlevel dielectric layer and on said exposed top contact portion of said metallic interconnect leads.
Claim 3
Dependent Claim 26 words
The method according to claim 1, said method further comprising forming an upper level dielectric layer on and substantially covering said inverted thin film resistor structure.
Claim 4
Dependent Claim 36 words
The method according to claim 1, wherein said inverted thin film resistor formation comprises the steps of: (a) depositing a resistive layer; and (b) photolithographically defining and etching a predetermined resistor pattern in said resistive layer.
Claim 5
Dependent Claim 26 words
The method according to claim 1, wherein said resistor has a length defined by a predetermined spacing between said top contact portion of said interconnect leads.
Claim 6
Dependent Claim 16 words
The method according to claim 1, wherein said supporting layer is a lower level dielectric layer.
Claim 7
Dependent Claim 14 words
The method according to claim 1, wherein said supporting layer is a semiconductor substrate.
Claim 8
Dependent Claim 28 words
The method according to claim 1, wherein said metallic interconnect layer is selected from the group consisting of: Al, Au, Cu, Ti, W, AlCu, TiW/Au, and combinations thereof.
Claim 9
Dependent Claim 26 words
The method according to claim 1, wherein said inverted thin film resistor is selected from the group consisting of: TaN, Cermet, TiN, TiW, and combinations thereof.
Claim 10
Dependent Claim 29 words
The method according to claim 1, wherein said interlevel dielectric layer is selected from the group consisting of: SiO 2 , Si 3 N 4 , and combinations thereof.
Claim 11
Dependent Claim 73 words
A microelectronic inverted thin film resistor structure comprising: a metallic interconnect layer having predetermined patterns delineating two or more metallic interconnect leads overlaying a supporting layer; a substantially planar interlevel dielectric layer overlaying said supporting layer, wherein an exposed portion of said leads extends above said dielectric layer; and an inverted thin film resistor overlaying a portion of said planar interlevel dielectric layer and overlaying said exposed portion of said metallic interconnect leads.
Claim 12
Dependent Claim 73 words
A microelectronic inverted thin film resistor structure comprising: a metallic interconnect layer having predetermined patterns delineating two or more metallic interconnect leads overlaying a supporting layer; a substantially planar interlevel dielectric layer overlaying said supporting layer, wherein an exposed portion of said leads extends above said dielectric layer; and an inverted thin film resistor overlaying a portion of said planar interlevel dielectric layer and overlaying said exposed portion of said metallic interconnect leads.
Claim 13
Dependent Claim 24 words
The structure of claim 10, said structure further comprising an upper level dielectric layer on and substantially covering said inverted thin film resistor structure.
Claim 14
Dependent Claim 24 words
The structure of claim 10, wherein said resistor has a length defined by a predetermined spacing between said exposed portion of said interconnect leads.
Claim 15
Dependent Claim 15 words
The structure of claim 10, wherein said supporting layer is a lower level dielectric layer.
Claim 16
Dependent Claim 13 words
The structure of claim 10, wherein said supporting layer is a semiconductor substrate.
Claim 17
Dependent Claim 27 words
The structure of claim 10, wherein said metallic interconnect layer is selected from the group consisting of: Al, Au, Cu, Ti, W, AlCu, TiW/Au, and combinations thereof.
Claim 18
Dependent Claim 25 words
The structure of claim 10, wherein said inverted thin film resistor is selected from the group consisting of: TaN, Cermet, TiN, TiW, and combinations thereof.
Claim 19
Dependent Claim 28 words
The structure of claim 10, wherein said interlevel dielectric layer is selected from the group consisting of: SiO 2 , Si 3 N 4 , and combinations thereof.

References Cited (Backward Citations)

US4676867A Cited
US4968964A Cited
US5367284A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1999-01-15 1999-07-17 2000-01-16 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2003-01-15 2003-07-17 2004-01-16 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2007-01-15 2007-07-17 2008-01-16 $7700.00 Window Closed / Lapsed

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