Phase-locked oscillator arrangement

Claim 1

A phase-locked oscillator arrangement in which a variable-frequency oscillator supplies an output signal controlled by a control voltage from a storage capacitance, which is charged by a charge pump circuit, which arrangement comprises a phase detector which has an input which receives a signal derived from the output signal of the variable-frequency oscillator, another input which receives a signal from a reference oscillator, and a reset input, the charge pump circuit comprising two current sources which each comprise a plurality of transistors operating in parallel and which, respectively, charge and discharge the storage capacitance, which charge pump circuit has two inputs, i.e. a first control input coupled to a first output of the phase detector, which supplies a switching signal called the up-command signal, which activates one of the current sources, and a second control input coupled to a second output of the phase detector, which supplies a switching signal called the down-command signal, which activates the other current source, in which arrangement the time interval during which these two command signals are simultaneously active is controlled by a reset signal from a logic gate which combines the up-command signal and the down-command signal, which reset signal is applied to the reset input of the phase detector after passage through a delay device, characterised in that the delay device comprises a current source called annexed current source, which is switchable and comprises a transistor forming a matched pair with a transistor of one of the current sources of the charge pump circuit, and comparison means for comparing the current supplied by said annexed current source with a given threshold current, which means supply the reset signal when this threshold is reached.