EP0449659B1
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Linearized three state phase detector
Assignee: Motorola Solutions Inc
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Filing: 1991-03-28
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Granted: 1995-09-20
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Expires: 2011-03-28
Abstract
Abstract A linearized three state phase detector (300) that exhibits a linear transfer function of phase to current or charge at and around the zero phase error region. The inputs to the D flip-flops (301 and 302) are tied to a logic high. The first flip-flop (301) is clocked with reference signal Fr while the other flip-flop (302) is clocked with a variable frequency feedback signal Fv. Fv is typically from a voltage controlled oscillator in a phase locked loop. The outputs of the flip-flops are ANDed together with the result of this operation going through a delay element (304) before reseting one of the flip-flops (301). The other flip-flop (302) is reset by the output of the AND gate (304) without the delay element (304). Each flip-flop output enables a charge pump - one negative polarity (306) and one positive polarity (305). The present invention (300) will maintain a lock condition in a phase locked loop by extending the DOWN pulse enabling the negative polarity charge pump (306) to the same width as the UP pulse that enables the positive pump (305). This will create a net zero charge from the present invention (300). <IMAGE>
Inventors
- 👤 Steven F. Gillig
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-06 08:31
CPC Classifications
H; H03; H03D; H03D13/00; H03D13/003; H03D13/004; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/085; H03L7/089; H03L7/0891
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
212 words
A phase detection apparatus for generating a phase difference signal for use in a phase locked loop, the phase detection apparatus having an input for a loop feedback signal, an input for a reference signal, and an output for the phase difference signal, the apparatus characterized by: a) first storage means (301) comprising a reset input, a first clock input, and an output; b) second storage means (302) comprising a reset input, a second clock input, and an output; c) means for logically combining (303) having a first input coupled to the output of the first storage means and a second input coupled to the output of the second storage means and an output coupled to the reset input of the second storage means; and the apparatus further characterized by: d) delaying means (304) having an input coupled to the output of the means for logically combining and an output coupled to the reset input of the first storage means (301); wherein the reference signal is coupled to the first clock input, the loop feedback signal is coupled to the second clock input and the output of the first storage means (301) and the output of the second storage means (302) are coupled to form the output for the phase difference signal.
Claim 2
Dependent Claim
81 words
The apparatus of claim 1 wherein the output of the first storage means (301) and the output of the second storage means (302) are coupled by a first current source (305) having an enable input coupled to the output of the first storage means (301) and a second current source (306) having an enable input coupled to the output of the second storage means (302), the first and second current sources coupled to form the output for the phase difference signal.
Claim 3
Dependent Claim
49 words
A phase detection apparatus according to claim 1 further comprising first current sourcing (305) means having an enable input coupled to the output of the first storage means (301); and second current sourcing means (306) having an enable input coupled to the output of the second storage means (302);
Claim 4
Independent Claim
33 words
The apparatus of any one of the preceding claims wherein the first (301) and the second (302) storage means are D type flip-flops that further comprise data inputs coupled to a logic high.
Claim 5
Dependent Claim
261 words
A phase detection apparatus for generating a phase difference signal for use in a phase locked loop, the phase detection apparatus having an input for a loop feedback signal, an input for a reference signal, and an output for the phase difference signal, the apparatus characterized by: a) first storage means having a reset input, a first clock input, and an output; b) first current sourcing means having an enable input coupled to the output of the first storage means; c) second storage means having a reset input, a second clock input, and an output; d) first delaying means (601) having an input and an output, the input coupled to the output of the second storage means; e) second current sourcing means having an enable input coupled to the output of the first delay means (601); f) means for logically combining having a first input coupled to the output of the first storage means and a second input coupled to the output of the second storage means and an output coupled to the reset input of the second storage means; and the apparatus further characterized by g) second delaying means having an input coupled to the output of the means for logically combining and an output coupled to the reset input of the first storage means; wherein the reference signal is coupled to the first clock input, the loop feedback signal is coupled to the second clock input and, the first current sourcing means and the second current sourcing means are coupled to form the output for the phase difference signal.
Claim 6
Dependent Claim
23 words
The apparatus of claim 5 wherein the second delaying means is coupled to the means for logically combining by a third delaying means.
Claim 7
Dependent Claim
244 words
A phase detection apparatus for generating a phase difference signal for use in a phase locked loop, the phase detection apparatus having an input for a loop feedback signal, an input for a reference signal, and an output for the phase difference signal, the apparatus characterized by: a) first storage means comprising a reset input, a first clock input, and an output; b) second storage means comprising a reset input, a second clock input, and an output; c) means for logically combining having a first input, a second input, and an output, the first input coupled to the output of the first storage means and the second input coupled to the output of the second storage means; d) first delaying means (801) having an input and an output, the input coupled to the output of the means for logically combining and the output coupled to the reset input of the first storage means; and the apparatus further characterized by e) second delaying means (802) having an input and an output, the input coupled to the output of the means for logically combining and an output coupled to the reset input of the second storage means; wherein the reference signal is coupled to the first clock input, the loop feedback signal is coupled to the second clock input and the output of the first storage means and the output of the second storage means are coupled to form the output for the phase difference signal.
Claim 8
Dependent Claim
29 words
The apparatus of claim 5, 6 or 7 wherein the first delaying means (801) has a delay that is larger than a delay of the second delaying means (802).
Claim 9
Independent Claim
20 words
The apparatus of any one of the preceding claims wherein the means for logically combining is a logical AND gate.
References Cited (Backward Citations)
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