Patent US3629097A successfully refreshed from Google Patents.
US5483645A
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US
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Cache access system for multiple requestors providing independent access to the cache arrays
Assignee: Advanced Micro Devices Inc
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Filing: 1993-02-22
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Granted: 1996-01-09
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Expires: 2013-02-22
Abstract
Abstract The present invention is an apparatus comprising first and second addressable arrays and an input for receiving address information related to the arrays. A first request line receives from a first source first request signals for access to the first and second arrays based on the address information. A second request line receives from a second source second request signals for access to the first and second arrays based on the address information. A processing circuit transmits the address information to the first and second addressable arrays in response to the first and second request signals based on a priority of the first and second request signals.
Inventors
- 👤 Thang M. Tran
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 23:07
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0806; G06F12/0815; G06F12/0831; G06F13/00; G06F13/14; G06F13/16; G06F13/18; G06F12/0844; G06F12/0855; G06F12/0857
Claims Analysis
Total Claims: 33
Claim 1
Independent Claim
201 words
A cache memory means apparatus comprising: a first addressable array means in the cache memory means; a second addressable array means in the cache memory means; first request receiving means, connected between an address bus means and said first and second addressable array means, for receiving first address information from said address bus means and for receiving first request signals from a first source means and for accessing said first and second array means using said first address information; second request receiving means, connected between said address bus means and said first and second addressable array means, for receiving second address information from said address bus means and for receiving second request signals from a second source means and for accessing said first and second means using said second address information; and transmitting means, connected between said first and second request means and said first and second addressable array means for selectively using said first and second request signals for simultaneously transmitting a portion of said first address information to one of said first or second addressable array means while a portion of said second address information is selectively transmitted to the other of said first and second addressable array means.
Claim 2
Dependent Claim
201 words
A cache memory means apparatus comprising: a first addressable array means in the cache memory means; a second addressable array means in the cache memory means; first request receiving means, connected between an address bus means and said first and second addressable array means, for receiving first address information from said address bus means and for receiving first request signals from a first source means and for accessing said first and second array means using said first address information; second request receiving means, connected between said address bus means and said first and second addressable array means, for receiving second address information from said address bus means and for receiving second request signals from a second source means and for accessing said first and second means using said second address information; and transmitting means, connected between said first and second request means and said first and second addressable array means for selectively using said first and second request signals for simultaneously transmitting a portion of said first address information to one of said first or second addressable array means while a portion of said second address information is selectively transmitted to the other of said first and second addressable array means.
Claim 3
Dependent Claim
87 words
An apparatus according to claim 1 wherein: said first request means includes means for latching said address information when said first request signals are active and outputting first latched address information, said transmitting means transmitting said first latched address information in response to said first request signals; said second request means includes means for latching said address information when said second request signals are active and outputting second latched address information, said transmitting means transmitting said second latched address information in response to said second request signals.
Claim 4
Dependent Claim
134 words
An apparatus according to claim 2 further including a third request receiving means, connected between said address bus means and said first and second addressable array means, for receiving third request signals from a third source means for accessing said first and second array means using said address information, said third request means including means for latching said address information when said third request signals are active and outputting third latched address information to said transmitting means, said transmitting means transmitting said third latched address information in response to said third request signals, said transmitting means transmitting said first, second and third latched address information to said first and second arrays in response to said first, second and third request signals based on a predetermined priority of said first, second and third request signals.
Claim 5
Dependent Claim
50 words
An apparatus according to claim 3 wherein said first request signals comprise a first tag and a first data request signal, said second request signals comprise a second tag and a second data request signal and said third request signals comprise a third tag and a third data request signal.
Claim 6
Dependent Claim
68 words
An apparatus according to claim 4 wherein said transmitting means includes: a first multiplexer control circuit receiving said first, second and third tag request signals and outputting first control signals; and a first multiplexer receiving said first, second and third latched address information and transmitting one of said first, second and third latched address information to said first addressable array means in response to said first control signals;
Claim 7
Dependent Claim
69 words
An apparatus according to claim 5 wherein said transmitting means further includes: a second multiplexer control circuit receiving said first, second and third data request signals and outputting second control signals; and a second multiplexer receiving said first, second and third latches address information and transmitting one of said first, second and third latched address information to said second addressable array means in response to said second control signals.
Claim 8
Dependent Claim
29 words
An apparatus according to claim 6 wherein said first and second multiplexer control circuits store said request signals and issue said request signals in order of their predetermined priority.
Claim 9
Dependent Claim
108 words
An apparatus according to claim 2 wherein said first request means receives a first signal for requesting access to said first addressable array means and a second signal for requesting access to said second addressable array means, and said means for latching address signals associated with said first request signals includes a first latch for latching address information in response to said first signal and a second latch for latching address information received from said first latch in response to said second signal, said first latch containing address information for said first addressable array means and said second latch containing address information for said second addressable array means.
Claim 10
Dependent Claim
108 words
An apparatus according to claim 8 wherein said second request means receives a third signal for requesting access to said first addressable array means and a fourth signal for requesting access to said second addressable array means, and said means for latching address signals associated with said second request signals includes a third latch for latching address information in response to said third signal and a fourth latch for latching address information received from said third latch in response to said fourth signal, said third latch containing address information for said first addressable array means and said second latch containing address information for said second addressable array means.
Claim 11
Dependent Claim
30 words
An apparatus according to claim 9 including means for comparing address information latched in said first latch to address information latched in said third latch, and outputting a comparison result.
Claim 12
Dependent Claim
61 words
An apparatus according to claim 9 including a separate address input for bypassing said request block latches for a speed path to said first and second addressable array means, said separate address input also being latched in said latching means for later use if priority prevents immediate access by said separate address input to said first and second addressable array means.
Claim 13
Dependent Claim
33 words
An apparatus according to claim 10 wherein said first request signals comprise processor request signals and said second request signals comprise bus watch request signals, said comparison result being a processor hit signal.
Claim 14
Dependent Claim
33 words
An apparatus according to claim 10 wherein said first request signals comprise command request signals and said second request signals comprise bus watch request signals, said comparison result being a command hit signal.
Claim 15
Dependent Claim
22 words
An apparatus according to claim 1 wherein said transmitting means established different request signal priorities for said first and second array means.
Claim 16
Dependent Claim
13 words
An apparatus according to claim 14 wherein said transmitting means includes a multiplexer.
Claim 17
Dependent Claim
21 words
An apparatus according to claim 1 wherein said first addressable array means comprises a store array of said cache memory means.
Claim 18
Dependent Claim
21 words
An apparatus according to claim 16 wherein said second addressable array means comprises a tag array of said cache memory means.
Claim 19
Dependent Claim
16 words
An apparatus according to claim 17 wherein said first source means comprises a processor request source.
Claim 20
Dependent Claim
16 words
An apparatus according to claim 18 wherein said second source means comprises a bus watching source.
Claim 21
Dependent Claim
16 words
An apparatus according to claim 18 wherein said second source means comprises a cache command source.
Claim 22
Independent Claim
196 words
A method of accessing means in a cache memory means, comprising the steps of: receiving address information for first and second addressable array means; receiving first request signals from a first source means for accessing said first and second array means, with a portion of said first request signals for accessing said first addressable array means and another portion of said first request signals for accessing said second addressable array means, and for latching first address information from an address bus means when one of said first request signals is active; receiving second request signals from a second source means for accessing said first and second array means, one with a portion of said second request signals for accessing said first addressable array means and another portion of said second request signals for accessing said second addressable array means, and for latching second address information when one of said second request signals is active; and selectively transmitting portions of first and second address information to said first and second addressable array means simultaneously via separate paths in response to said first and second request signals based on a priority of said first and second request signals.
Claim 23
Independent Claim
196 words
A method of accessing means in a cache memory means, comprising the steps of: receiving address information for first and second addressable array means; receiving first request signals from a first source means for accessing said first and second array means, with a portion of said first request signals for accessing said first addressable array means and another portion of said first request signals for accessing said second addressable array means, and for latching first address information from an address bus means when one of said first request signals is active; receiving second request signals from a second source means for accessing said first and second array means, one with a portion of said second request signals for accessing said first addressable array means and another portion of said second request signals for accessing said second addressable array means, and for latching second address information when one of said second request signals is active; and selectively transmitting portions of first and second address information to said first and second addressable array means simultaneously via separate paths in response to said first and second request signals based on a priority of said first and second request signals.
Claim 24
Independent Claim
220 words
An apparatus, comprising: a cache memory means having an independently addressable tag array means and an independently addressable store array means; a plurality of access request line means for receiving access request signals from different source means; a plurality of sets of latch means connected to an address bus means for receiving address signals for said tag and store array means from said address bus means, each latch means of each set of said plurality of sets of latch means receiving one of said address signals, one of said sets of said plurality of sets of latch means being associated with each of said access request line means for latching address information; said access request line means and associated said plurality of sets of latch means comprising a first group associated with said tag array means and a second group associated with said store array means; first means for selectively passing address information in said plurality of sets of latch means associated with access request line means in said first group to said tag array means; and second means for selectively passing address information in said plurality of sets of latch means associated with access request line means in said second group to said store array means via a path independent of said first means for selectively passing address information.
Claim 25
Independent Claim
220 words
An apparatus, comprising: a cache memory means having an independently addressable tag array means and an independently addressable store array means; a plurality of access request line means for receiving access request signals from different source means; a plurality of sets of latch means connected to an address bus means for receiving address signals for said tag and store array means from said address bus means, each latch means of each set of said plurality of sets of latch means receiving one of said address signals, one of said sets of said plurality of sets of latch means being associated with each of said access request line means for latching address information; said access request line means and associated said plurality of sets of latch means comprising a first group associated with said tag array means and a second group associated with said store array means; first means for selectively passing address information in said plurality of sets of latch means associated with access request line means in said first group to said tag array means; and second means for selectively passing address information in said plurality of sets of latch means associated with access request line means in said second group to said store array means via a path independent of said first means for selectively passing address information.
Claim 26
Dependent Claim
98 words
An apparatus according to claim 22 wherein said request line means from an identical source means are arranged together with their associated set of said plurality of sets of latches and wherein a first request line means from said identical source means is connected to gate address information to a first latch means of a pair of latch means, and a second request line from said identical source means is connected to gate said address information from said first latch means of said pair of latch means to the second latch means of said pair of latch means.
Claim 27
Dependent Claim
19 words
An apparatus according to claim 23 wherein said first means for selectively passing address information comprises a first multiplexer.
Claim 28
Dependent Claim
19 words
An apparatus according to claim 24 wherein said second means for selectively passing address information comprises a second multiplexer.
Claim 29
Dependent Claim
19 words
An apparatus according to claim 25 including means for controlling said first multiplexer according to a first priority scheme.
Claim 30
Dependent Claim
19 words
An apparatus according to claim 26 including means for controlling said second multiplexer according to a second priority scheme.
Claim 31
Dependent Claim
162 words
A cache memory means apparatus, comprising: a first addressable array means in said cache memory means; a second addressable array means in said cache memory means; first request receiving means for receiving a first and second request signal from a first source means for accessing said first and second addressable array means, respectively; a second request receiving means for receiving a third and fourth request signal from a second source means for accessing said first and second addressable array means respectively; a plurality of address means, one of said plurality of address means being respectively associated with said first and second request receiving means, for receiving address information for said first and second addressable array means; and first and second transmitting means, receiving address information from each of said plurality of address means, for selectively transmitting said address information to said first and second addressable array means respectively, according to a predetermined priority of said first, second, third and fourth request signals.
Claim 32
Dependent Claim
162 words
A cache memory means apparatus, comprising: a first addressable array means in said cache memory means; a second addressable array means in said cache memory means; first request receiving means for receiving a first and second request signal from a first source means for accessing said first and second addressable array means, respectively; a second request receiving means for receiving a third and fourth request signal from a second source means for accessing said first and second addressable array means respectively; a plurality of address means, one of said plurality of address means being respectively associated with said first and second request receiving means, for receiving address information for said first and second addressable array means; and first and second transmitting means, receiving address information from each of said plurality of address means, for selectively transmitting said address information to said first and second addressable array means respectively, according to a predetermined priority of said first, second, third and fourth request signals.
Claim 33
Dependent Claim
131 words
An apparatus according to claim 28 wherein: said first request receiving means includes means for latching said address information according to said first and second request signals and outputting first and second latched address information to said first and second transmitting means; said second request receiving means includes means for latching address information according to said third and fourth request signals and outputting third and fourth latched address information to said first and second transmitting means; said first transmitting means transmitting said first and third latched address information to said first addressable array means, in response to said first and third request signals; and said second transmitting means transmitting said second and fourth latched address information to said second addressable array means, in response to said second and fourth request signals.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-01-08 | 1999-07-10 | 2000-01-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-01-08 | 2003-07-10 | 2004-01-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-01-08 | 2007-07-10 | 2008-01-09 | $7700.00 | Window Closed / Lapsed |