Patent US5483640A successfully refreshed from Google Patents.
US5483640A
Expired / Lapsed
US
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System for managing data flow among devices by storing data and structures needed by the devices and transferring configuration information from processor to the devices
Assignee: HP Inc
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Filing: 1993-02-26
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Granted: 1996-01-09
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Expires: 2013-02-26
Abstract
Abstract An internetwork device which manages the flow of packets of I/O data among a plurality of network interface devices includes a bus coupled to the plurality of network interface devices, a core memory storing only packets of I/O data and control structures needed by the plurality of network interface devices, and a processor including local memory isolated from the core memory storing routines and internetwork information involved in updating control structures and control fields in the packets of I/O data to direct movements of packets of I/O data among the plurality of network interface devices. A bus-memory interface is provided through which transfers of packets of I/O/data and control structures used by the plurality of network interface devices are conducted between the core memory and the bus. A processor-memory interface is provided through which transfers of data to or from control structures or control fields in packets of I/O data are conducted between the core memory and the processor. Finally, a processor-bus interface is included through which configuration information concerning control structures and I/O data buffers in the core memory are transferred between the plurality of network interface devices and the processor across the bus. The processor-bus and processor-memory interfaces include structures for decoupling processor accesses to configuration stores in the plurality network interface devices and to the core memory from contention with bus-memory interface transfers between the core memory and the plurality of network interface devices.
Inventors
- 👤 Mark S. Isfeld
- 👤 Bruce W. Mitchell
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 23:22
CPC Classifications
H; H04; H04L; H04L49/00; H04L49/90; H04L49/9057
Claims Analysis
Total Claims: 33
Claim 1
Independent Claim
185 words
An apparatus for managing data flow among a plurality of input/output devices, comprising: a core memory storing I/O data and control structures needed by the input/output devices; a processor, including local memory isolated from the core memory and storing control information and instructions used by routines executed by the processor managing data flow among the input/output devices; a first memory interface responsive to the plurality of input/output devices, including means, in communication with the plurality of input/output devices and the core memory, for transferring I/O data and control data between the input/output devices in the plurality of input/output devices and the I/O data and control structures in the core memory; a second memory interface responsive to the processor, including means in communication with the processor and the core memory, for transferring control data between control structures and I/O data in the core memory and the processor, and; a configuration interface, coupled with the plurality of input/output devices and the processor, for transferring control and status information concerning control structures and I/O data in the core memory between the plurality of input/output devices and the processor.
Claim 2
Independent Claim
185 words
An apparatus for managing data flow among a plurality of input/output devices, comprising: a core memory storing I/O data and control structures needed by the input/output devices; a processor, including local memory isolated from the core memory and storing control information and instructions used by routines executed by the processor managing data flow among the input/output devices; a first memory interface responsive to the plurality of input/output devices, including means, in communication with the plurality of input/output devices and the core memory, for transferring I/O data and control data between the input/output devices in the plurality of input/output devices and the I/O data and control structures in the core memory; a second memory interface responsive to the processor, including means in communication with the processor and the core memory, for transferring control data between control structures and I/O data in the core memory and the processor, and; a configuration interface, coupled with the plurality of input/output devices and the processor, for transferring control and status information concerning control structures and I/O data in the core memory between the plurality of input/output devices and the processor.
Claim 3
Dependent Claim
23 words
The apparatus of claim 1, wherein the second memory interface includes a read cache for reads by the processor from the core memory.
Claim 4
Dependent Claim
22 words
The apparatus of claim 1, wherein in the second interface includes a buffer for writes from the processor to the core memory.
Claim 5
Dependent Claim
47 words
The apparatus of claim 1, wherein the second memory interface includes: means, coupled to the processor and the core memory, for decoupling processor accesses to the core memory from contention with transfers between the core memory and the plurality of input/output devices through the first memory interface.
Claim 6
Dependent Claim
23 words
The apparatus of claim 1, wherein the core memory stores only I/O data and control structures needed by the plurality of input/output devices.
Claim 7
Dependent Claim
59 words
The apparatus of claim 1, wherein the second memory interface includes: means, coupled to the processor, the plurality of input/output devices and the core memory, for decoupling processor accesses to the plurality of input/output devices and to the core memory from contention with transfers between the core memory and the plurality of input/output devices through the first memory interface.
Claim 8
Dependent Claim
36 words
The apparatus of claim 1, wherein the means in the first memory interface for transferring data between the plurality of input/output devices and the core memory comprises a bus coupled to the plurality of input/output devices.
Claim 9
Independent Claim
168 words
An apparatus for managing an interface among a plurality of network interface devices coupled to respective networks communicating packets of I/O data, comprising: a bus coupled to the plurality of network interface devices; a core memory; a processor including local memory storing control information and routines executed by the processor involved in moving packets of I/O data among the plurality of network interface devices; a bus-memory interface, including means, coupled to the bus and the core memory, for transferring packets of I/O data and control data used by the plurality of network interface devices between the bus and the core memory; a processor-memory interface, including means, coupled to the processor and the core memory, for transferring control data used by the plurality of network interface devices between the core memory and the processor, and; a configuration interface, coupled with the bus and the processor, for transferring configuration information concerning control structures and I/O data in the core memory between the plurality of network interface devices and the processor.
Claim 10
Independent Claim
168 words
An apparatus for managing an interface among a plurality of network interface devices coupled to respective networks communicating packets of I/O data, comprising: a bus coupled to the plurality of network interface devices; a core memory; a processor including local memory storing control information and routines executed by the processor involved in moving packets of I/O data among the plurality of network interface devices; a bus-memory interface, including means, coupled to the bus and the core memory, for transferring packets of I/O data and control data used by the plurality of network interface devices between the bus and the core memory; a processor-memory interface, including means, coupled to the processor and the core memory, for transferring control data used by the plurality of network interface devices between the core memory and the processor, and; a configuration interface, coupled with the bus and the processor, for transferring configuration information concerning control structures and I/O data in the core memory between the plurality of network interface devices and the processor.
Claim 11
Dependent Claim
22 words
The apparatus of claim 8, wherein the processor-memory interface includes a read cache for reads by the processor from the core memory.
Claim 12
Dependent Claim
22 words
The apparatus of claim 8, wherein in the processor-memory interface includes a buffer for writes from the processor to the core memory.
Claim 13
Dependent Claim
54 words
The apparatus of claim 8, further including: means, coupled to the processor, the bus and the core memory, for decoupling processor accesses to configuration information in the plurality of network interface devices and to the core memory from contention with bus-memory interface transfers between the core memory and the plurality of network interface devices.
Claim 14
Dependent Claim
24 words
The apparatus of claim 8, wherein the core memory stores only I/O data and control structures needed by the plurality of network interface devices.
Claim 15
Dependent Claim
44 words
The apparatus of claim 8, wherein the processor-memory interface includes: means, coupled to the processor and the core memory, for decoupling processor accesses to the core memory from contention with bus-memory interface transfers between the core memory and the plurality of network interface devices.
Claim 16
Dependent Claim
63 words
The apparatus of claim 8, wherein the processor-memory interface includes: a read cache, coupled with the core memory, for storing words from a plurality of sequential addresses in the core memory for reads by the processor from the core memory; and a cache manager maintaining words in the read cache with burst mode transfers from the plurality of sequential addresses in core memory.
Claim 17
Dependent Claim
63 words
The apparatus of claim 8, wherein the processor-memory interface includes: a write buffer, coupled to the core memory, for storing words for writes from the processor to plurality of sequential addresses in the core memory; and a buffer manager writing words from the write buffer to the core memory with burst mode transfers to the plurality of sequential addresses in the core memory.
Claim 18
Independent Claim
211 words
An apparatus for managing an interface among a plurality of network interface devices coupled to respective networks communicating packets of I/O data, comprising: a bus coupled to the plurality of network interface devices; a core memory storing only packets of I/O data and control structures needed by the plurality of network interface devices; a processor including local memory isolated from the core memory storing routines executed by the processor and internetwork control information involved in updating control structures or control fields in packets of I/O data to direct movement of packets of I/O data among the plurality of network interface devices; a bus-memory interface, including means, coupled to the bus and the core memory, for transferring packets of I/O data and control structures used by the plurality of network interface devices between the core memory and the bus; a processor-memory interface, including means, coupled to the processor and the core memory, for transferring data to or from control structures or control fields in packets of I/O data between the core memory and the processor; and a processor-bus interface, including means, coupled to the processor and the bus, for transferring configuration information concerning control structures and I/O data in the core memory between the plurality of network interface devices and the processor.
Claim 19
Independent Claim
211 words
An apparatus for managing an interface among a plurality of network interface devices coupled to respective networks communicating packets of I/O data, comprising: a bus coupled to the plurality of network interface devices; a core memory storing only packets of I/O data and control structures needed by the plurality of network interface devices; a processor including local memory isolated from the core memory storing routines executed by the processor and internetwork control information involved in updating control structures or control fields in packets of I/O data to direct movement of packets of I/O data among the plurality of network interface devices; a bus-memory interface, including means, coupled to the bus and the core memory, for transferring packets of I/O data and control structures used by the plurality of network interface devices between the core memory and the bus; a processor-memory interface, including means, coupled to the processor and the core memory, for transferring data to or from control structures or control fields in packets of I/O data between the core memory and the processor; and a processor-bus interface, including means, coupled to the processor and the bus, for transferring configuration information concerning control structures and I/O data in the core memory between the plurality of network interface devices and the processor.
Claim 20
Dependent Claim
44 words
The apparatus of claim 16, wherein the processor-memory interface includes: means, coupled to the processor and the core memory, for decoupling processor accesses to the core memory from contention with bus-memory interface transfers between the core memory and the plurality of network interface devices.
Claim 21
Dependent Claim
28 words
The apparatus of claim 17, wherein the means for decoupling includes a read cache, coupled with the core memory, for reads by the processor from the core memory.
Claim 22
Dependent Claim
26 words
The apparatus of claim 18, further including a cache manager maintaining data from a plurality of sequential addresses from the core memory in the read cache.
Claim 23
Dependent Claim
28 words
The apparatus of claim 17, wherein the means for decoupling includes a write buffer, coupled with the core memory, for writes from the processor to the core memory.
Claim 24
Dependent Claim
52 words
The apparatus of claim 17, wherein the means for decoupling includes: a read cache, coupled with the bus and the core memory, for reads by the processor from the core memory and the bus; and a write buffer, coupled with the core memory, for writes from the processor to the core memory.
Claim 25
Dependent Claim
26 words
The apparatus of claim 21, further including a cache manager maintaining data from a plurality of sequential addresses from the core memory in the read cache.
Claim 26
Dependent Claim
54 words
The apparatus of claim 16, further including: means, coupled to the processor, the bus and the core memory, for decoupling processor accesses to configuration stores in the plurality of network interface devices and to the core memory from contention with bus-memory interface transfers between the core memory and the plurality of network interface devices.
Claim 27
Dependent Claim
41 words
The apparatus of claim 23, wherein the means for decoupling includes a read cache, coupled with the bus and core memory, for reads by the processor from configuration stores in the plurality of network interface devices and from the core memory.
Claim 28
Dependent Claim
36 words
The apparatus of claim 24, further including a cache manager maintaining data from a plurality of sequential addresses from the core memory or configuration stores in the plurality of network interface devices in the read cache.
Claim 29
Dependent Claim
43 words
The apparatus of claim 23, wherein in the means for decoupling includes a write buffer, coupled with the bus and the core memory, for writes from the processor to configuration stores in the plurality of network interface devices and to the core memory.
Claim 30
Dependent Claim
73 words
The apparatus of claim 23, wherein the means for decoupling includes: a read cache, coupled with the bus and core memory, for reads by the processor from configuration stores in the plurality of network interface devices and from the core memory; and a write buffer, coupled with the bus and the core memory, for writes from the processor to configuration stores in the plurality of network interface devices and to the core memory.
Claim 31
Dependent Claim
36 words
The apparatus of claim 27, further including a cache manager maintaining data from a plurality of sequential addresses from the core memory or configuration stores in the plurality of network interface devices in the read cache.
Claim 32
Dependent Claim
64 words
The apparatus of claim 16, wherein the processor-memory interface includes: a read cache, coupled with the core memory, for storing words from a plurality of sequential addresses in the core memory for reads by the processor from the core memory; and a cache manager maintaining words in the read cache with burst mode transfers from the plurality of sequential addresses in the core memory.
Claim 33
Dependent Claim
63 words
The apparatus of claim 16, wherein the processor-memory interface includes: a write buffer, coupled to the core memory, for storing words for writes from the processor to plurality of sequential addresses in the core memory; and a buffer manager writing words from the write buffer to the core memory with burst mode transfers to the plurality of sequential addresses in the core memory.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-01-08 | 1999-07-10 | 2000-01-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-01-08 | 2003-07-10 | 2004-01-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-01-08 | 2007-07-10 | 2008-01-09 | $7700.00 | Window Closed / Lapsed |