Patent US5483484A successfully refreshed from Google Patents.
US5483484A
Expired / Lapsed
US
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Electrically erasable programmable read-only memory with an array of one-transistor memory cells
Assignee: Toshiba Corp
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Filing: 1994-05-18
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Granted: 1996-01-09
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Expires: 2014-05-18
Abstract
Abstract A floating gate tunneling metal oxide semiconductor transistor is formed on a semiconductive substrate as a cell of electrically erasable programmable read-only memory. The transistor includes a source and a drain spaced apart to define a channel region therebetween in the substrate. An insulated floating gate at least partially overlies the channel region and is capacitively coupled with the substrate. A control gate is insulatively disposed above the conductive layer and spans the channel region. The withstanding voltage of the drain is specifically set to range from a first voltage adapted to be applied to the drain during a read operation to a second voltage applied thereto for forcing the conductive layer to discharge.
Inventors
- 👤 Tetsuo Endoh
- 👤 Riichiro Shirota
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 23:54
CPC Classifications
H; H10; H10B; H10B41/00; H10B41/30; H10B41/35; G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/10; G11C16/14; G11C16/16; H10B41/40; H10B41/41; H10B69/00; H10D; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0128
Claims Analysis
Total Claims: 40
Claim 1
Independent Claim
101 words
An electrically erasable and programmable transistor comprising: a semiconductive substrate; a source and a drain spaced apart to define a channel region therebetween in said substrate; an insulated conductive layer at least partially overlying the channel region and being capacitively coupled with said substrate; a control gate insulatively disposed above the conductive layer and spanning the channel region; and means for maintaining a withstanding voltage between said drain and said source between a first voltage adapted to be applied to said drain during a read operation and a second voltage applied to said drain for forcing said conductive layer to discharge.
Claim 2
Dependent Claim
101 words
An electrically erasable and programmable transistor comprising: a semiconductive substrate; a source and a drain spaced apart to define a channel region therebetween in said substrate; an insulated conductive layer at least partially overlying the channel region and being capacitively coupled with said substrate; a control gate insulatively disposed above the conductive layer and spanning the channel region; and means for maintaining a withstanding voltage between said drain and said source between a first voltage adapted to be applied to said drain during a read operation and a second voltage applied to said drain for forcing said conductive layer to discharge.
Claim 3
Dependent Claim
37 words
A transistor according to claim 1, wherein said drain is doped with an impurity at a specific density which causes said withstanding voltage to be potentially greater than the first voltage and less than the second voltage.
Claim 4
Dependent Claim
20 words
A transistor according to claim 2, wherein said source and said drain are opposite in conductivity type to said substrate.
Claim 5
Dependent Claim
25 words
A transistor according to claim 3, wherein said source and drain are spaced apart at a certain distance which is on the order of submicrons.
Claim 6
Dependent Claim
36 words
A transistor according to claim 4, further comprising: a dielectric layer between said substrate and said conductive layer, said dielectric layer being thin enough to allow charged particles to tunnel to or from said conductive layer.
Claim 7
Dependent Claim
23 words
A transistor according to claim 5, wherein said source and said drain are substantially self-aligned with said conductive layer and said control gate.
Claim 8
Dependent Claim
20 words
A transistor according to claim 1, wherein electrons are discharged from said conductive layer to at least said channel region.
Claim 9
Dependent Claim
57 words
A transistor according to claim 1, wherein said control gate has a specific length so as to maintain the withstanding voltage between said drain and said source between the first voltage adapted to be applied to said drain during the read operation and the second voltage applied to said drain for forcing said conductive layer to discharge.
Claim 10
Dependent Claim
64 words
A transistor according to claim 1, wherein an impurity densities of said channel region and said substrate have respective specific amounts so as to maintain the withstanding voltage between said drain and said source between the first voltage adapted to be applied to said drain during the read operation and the second voltage applied to said drain for forcing said conductive layer to discharge.
Claim 11
Dependent Claim
37 words
A transistor according to claim 7, wherein said drain is doped with an impurity at a specific density which causes said withstanding voltage to be potentially greater than the first voltage and less than the second voltage.
Claim 12
Dependent Claim
57 words
A transistor according to claim 7, wherein said control gate has a specific length so as to maintain the withstanding voltage between said drain and said source between the first voltage adapted to be applied to said drain during the read operation and the second voltage applied to said drain for forcing said conductive layer to discharge.
Claim 13
Dependent Claim
64 words
A transistor according to claim 7, wherein an impurity densities of said channel region and said substrate have respective specific amounts so as to maintain the withstanding voltage between said drain and said source between the first voltage adapted to be applied to said drain during the read operation and the second voltage applied to said drain for forcing said conductive layer to discharge.
Claim 14
Dependent Claim
101 words
An electrically erasable and programmable transistor comprising: a semiconductive substrate; a source and a drain spaced apart to define a channel region therebetween in said substrate; an insulated conductive layer at least partially overlying the channel region and being capacitively coupled with said substrate; a control gate insulatively disposed above the conductive layer and spanning the channel region; and means for maintaining a punch-through voltage between said drain and said source between a first voltage adapted to be applied to said drain during a read operation and a second voltage applied to said drain for forcing said conductive layer to discharge.
Claim 15
Dependent Claim
101 words
An electrically erasable and programmable transistor comprising: a semiconductive substrate; a source and a drain spaced apart to define a channel region therebetween in said substrate; an insulated conductive layer at least partially overlying the channel region and being capacitively coupled with said substrate; a control gate insulatively disposed above the conductive layer and spanning the channel region; and means for maintaining a punch-through voltage between said drain and said source between a first voltage adapted to be applied to said drain during a read operation and a second voltage applied to said drain for forcing said conductive layer to discharge.
Claim 16
Dependent Claim
20 words
A transistor according to claim 13, wherein electrons are discharged from said conductive layer to at least said channel region.
Claim 17
Dependent Claim
37 words
A transistor according to claim 13, wherein said drain is doped with an impurity at a specific density which causes said punch-through voltage to be potentially greater than the first voltage and less than the second voltage.
Claim 18
Dependent Claim
57 words
A transistor according to claim 13, wherein said control gate has a specific length so as to maintain the punch-through voltage between said drain and said source between the first voltage adapted to be applied to said drain during the read operation and the second voltage applied to said drain for forcing said conductive layer to discharge.
Claim 19
Dependent Claim
64 words
A transistor according to claim 13, wherein an impurity densities of said channel region and said substrate have respective specific amounts so as to maintain the punch-through voltage between said drain and said source between the first voltage adapted to be applied to said drain during the read operation and the second voltage applied to said drain for forcing said conductive layer to discharge.
Claim 20
Dependent Claim
37 words
A transistor according to claim 14, wherein said drain is doped with an impurity at a specific density which causes said punch-through voltage to be potentially greater than the first voltage and less than the second voltage.
Claim 21
Dependent Claim
57 words
A transistor according to claim 14, wherein said control gate has a specific length so as to maintain the punch-through voltage between said drain and said source between the first voltage adapted to be applied to said drain during the read operation and the second voltage applied to said drain for forcing said conductive layer to discharge.
Claim 22
Dependent Claim
64 words
A transistor according to claim 14, wherein an impurity densities of said channel region and said substrate have respective specific amounts so as to maintain the punch-through voltage between said drain and said source between the first voltage adapted to be applied to said drain during the read operation and the second voltage applied to said drain for forcing said conductive layer to discharge.
Claim 23
Dependent Claim
119 words
An electrically erasable and programmable transistor comprising: a semiconductive substrate; a source and a drain spaced apart to define a channel region therebetween in said substrate; an insulated conductive layer at least partially overlying the channel region and being capacitively coupled with said substrate; a control gate insulatively disposed above the conductive layer and spanning the channel region; and means for causing a potential of said source to differ from a potential of said drain when a first voltage is applied to said drain, and causing the potential of said source to be equal to the potential of said drain when said drain is applied with a voltage higher than the first voltage and less than the second voltage.
Claim 24
Dependent Claim
119 words
An electrically erasable and programmable transistor comprising: a semiconductive substrate; a source and a drain spaced apart to define a channel region therebetween in said substrate; an insulated conductive layer at least partially overlying the channel region and being capacitively coupled with said substrate; a control gate insulatively disposed above the conductive layer and spanning the channel region; and means for causing a potential of said source to differ from a potential of said drain when a first voltage is applied to said drain, and causing the potential of said source to be equal to the potential of said drain when said drain is applied with a voltage higher than the first voltage and less than the second voltage.
Claim 25
Dependent Claim
20 words
A transistor according to claim 21, wherein electrons are discharged from said conductive layer to at least said channel region.
Claim 26
Dependent Claim
77 words
A transistor according to claim 21, wherein said drain is doped with an impurity at a specific density which causes the potential of said source to differ from the potential of said drain when the first voltage is applied to said drain, and causes the potential of said source to be equal to the potential of said drain when said drain is applied with the voltage higher than the first voltage and less than the second voltage.
Claim 27
Dependent Claim
75 words
A transistor according to claim 21, wherein said control gate has a specific length so as to cause the potential of said source to differ from the potential of said drain when the first voltage is applied to said drain, and cause the potential of said source to be equal to the potential of said drain when said drain Is applied with the voltage higher than the first voltage and less than the second voltage.
Claim 28
Dependent Claim
82 words
A transistor according to claim 21, wherein an impurity densities of said channel region and said substrate have respective specific amounts so as to cause the potential of said source to differ from the potential of said drain when the first voltage is applied to said drain, and cause the potential of said source to be equal to the potential of said drain when said drain is applied with the voltage higher than the first voltage and less than the second voltage.
Claim 29
Dependent Claim
77 words
A transistor according to claim 22, wherein said drain is doped with an impurity at a specific density which causes the potential of said source to differ from the potential of said drain when the first voltage is applied to said drain, and causes the potential of said source to be equal to the potential of said drain when said drain is applied with the voltage higher than the first voltage and less than the second voltage.
Claim 30
Dependent Claim
75 words
A transistor according to claim 22, wherein said control gate has a specific length so as to cause the potential of said source to differ from the potential of said drain when the first voltage is applied to said drain, and cause the potential of said source to be equal to the potential of said drain when said drain is applied with the voltage higher than the first voltage and less than the second voltage.
Claim 31
Dependent Claim
82 words
A transistor according to claim 22, wherein an impurity densities of said channel region and said substrate have respective specific amounts so as to cause the potential of said source to differ from the potential of said drain when the first voltage is applied to said drain, and cause the potential of said source to be equal to the potential of said drain when said drain is applied with the voltage higher than the first voltage and less than the second voltage.
Claim 32
Dependent Claim
126 words
An electrically erasable and programmable transistor comprising: a semiconductive substrate; a source and a drain spaced apart to define a channel region therebetween in said substrate; an insulated conductive layer at least partially overlying the channel region and being capacitively coupled with said substrate; a control gate insulatively disposed above the conductive layer and spanning the channel region; and means for causing potentials of said source and said channel region to differ from a potential of said drain when a first voltage is applied to said drain, and causing the potentials of said source and said channel region to be equal to the potential of said drain when said drain is applied with a voltage higher than the first voltage and less than the second voltage.
Claim 33
Dependent Claim
126 words
An electrically erasable and programmable transistor comprising: a semiconductive substrate; a source and a drain spaced apart to define a channel region therebetween in said substrate; an insulated conductive layer at least partially overlying the channel region and being capacitively coupled with said substrate; a control gate insulatively disposed above the conductive layer and spanning the channel region; and means for causing potentials of said source and said channel region to differ from a potential of said drain when a first voltage is applied to said drain, and causing the potentials of said source and said channel region to be equal to the potential of said drain when said drain is applied with a voltage higher than the first voltage and less than the second voltage.
Claim 34
Dependent Claim
20 words
A transistor according to claim 29, wherein electrons are discharged from said conductive layer to at least said channel region.
Claim 35
Dependent Claim
85 words
A transistor according to claim 29, wherein said drain is doped with an impurity at a specific density which causes the potentials of said source and said channel region to differ from the potential of said drain when the first voltage is applied to said drain, and causes the potentials of said source and said channel region to be equal to the potential of said drain when said drain is applied with the voltage higher than the first voltage and less than the second voltage.
Claim 36
Dependent Claim
83 words
A transistor according to claim 29, wherein said control gate has a specific length so as to cause the potentials of said source and said channel region to differ from the potential of said drain when the first voltage is applied to said drain, and cause the potentials of said source and said channel region to be equal to the potential of said drain when said drain is applied with the voltage higher than the first voltage and less than the second voltage.
Claim 37
Dependent Claim
90 words
A transistor according to claim 29, wherein an impurity densities of said channel region and said substrate have respective specific amounts so as to cause the potentials of said source and said channel region to differ from the potential of said drain when the first voltage Is applied to said drain, and cause the potentials of said source and said channel region to be equal to the potential of said drain when said drain is applied with the voltage higher than the first voltage and less than the second voltage.
Claim 38
Dependent Claim
85 words
A transistor according to claim 30, wherein said drain is doped with an impurity at a specific density which causes the potentials of said source and said channel region to differ from the potential of said drain when the first voltage is applied to said drain, and causes the potentials of said source and said channel region to be equal to the potential of said drain when said drain is applied with the voltage higher than the first voltage and less than the second voltage.
Claim 39
Dependent Claim
83 words
A transistor according to claim 30, wherein said control gate has a specific length so as to cause the potentials of said source and said channel region to differ from the potential of said drain when the first voltage is applied to said drain, and cause the potentials of said source and said channel region to be equal to the potential of said drain when said drain is applied with the voltage higher than the first voltage and less than the second voltage.
Claim 40
Dependent Claim
90 words
A transistor according to claim 30, wherein an impurity densities of said channel region and said substrate have respective specific amounts so as to cause the potentials of said source and said channel region to differ from the potential of said drain when the first voltage is applied to said drain, and cause the potentials of said source and said channel region to be equal to the potential of said drain when said drain is applied with the voltage higher than the first voltage and less than the second voltage.
References Cited (Backward Citations)
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1999-01-08 | 1999-07-10 | 2000-01-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-01-08 | 2003-07-10 | 2004-01-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-01-08 | 2007-07-10 | 2008-01-09 | $7700.00 | Window Closed / Lapsed |