Patent US5483082A successfully refreshed from Google Patents.
US5483082A
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Thin film transistor matrix device
Assignee: Sharp Corp
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Filing: 1993-12-28
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Granted: 1996-01-09
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Expires: 2013-12-28
Abstract
Abstract A thin film transistor matrix device comprises a transparent insulating substrate, a thin film transistor unit, a picture element unit, a storage capacitance unit, a gate terminal unit, and a drain terminal unit, the storage capacitance unit including a storage capacitance electrode formed on the transparent insulating substrate and formed of a metal layer of the same material as the gate electrode; a dielectric film formed on the storage capacitance electrode and formed of an insulating film common with the gate insulating film and a non-doped semiconductor layer of the same material as the semiconductor active layer; and a counter electrode formed on the dielectric film and formed of a doped semiconductor layer of the same material as the semiconductor contact layer and a metal layer of the same material as the source electrode and the drain electrode, the counter electrode being connected to the picture element electrode through a contact hole opened in a protecting film common with the passivation film. Thus, the fabrication process of the TFT matrix device can be simplified, and lower costs can be realized. Characteristic changes of the storage capacitance can be prevented, and yields and reliability can be improved.
Inventors
- 👤 Hideaki Takizawa
- 👤 Yasuhiro Nasu
- 👤 Kazuhiro Watanabe
- 👤 Shiro Hirota
- 👤 Kazuo Nonaka
- 👤 Seii Sato
- 👤 Teiji Majima
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 15:44
CPC Classifications
G; G02; G02F; G02F1/00; G02F1/01; G02F1/13; G02F1/133; G02F1/1333; G02F1/1345; G02F1/13458; G02F1/136; G02F1/1362; G02F1/136213; H; H10; H10D; H10D86/00; G02F1/133357; G02F1/13452
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
228 words
A thin film transistor matrix device comprising: a transparent insulating substrate; a thin film transistor unit including a gate electrode formed on the transparent insulating substrate; a semiconductor active layer formed on the gate electrode through a gate insulating film; a source electrode and a drain electrode formed opposed to each other on the semiconductor active layer respectively through a semiconductor contact layer; and a passivation film covering the source electrode and the drain electrode; a picture element unit including a picture element electrode formed in connection with the source electrode of the thin film transistor unit; and a storage capacitance unit connected to the picture element electrode of the picture element unit, the storage capacitance unit including a storage capacitance electrode formed on the transparent insulating substrate and formed of a metal layer of the same material as the gate electrode; a dielectric film formed on the storage capacitance electrode and formed of an insulating film common with the gate insulating film and a non-doped semiconductor layer of the same material as the semiconductor active layer; and a counter electrode formed on the dielectric film and formed of a doped semiconductor layer of the same material as the semiconductor contact layer and a metal layer of the same material as the source electrode and the drain electrode, the counter electrode being connected to the picture element electrode.
Claim 2
Dependent Claim
228 words
A thin film transistor matrix device comprising: a transparent insulating substrate; a thin film transistor unit including a gate electrode formed on the transparent insulating substrate; a semiconductor active layer formed on the gate electrode through a gate insulating film; a source electrode and a drain electrode formed opposed to each other on the semiconductor active layer respectively through a semiconductor contact layer; and a passivation film covering the source electrode and the drain electrode; a picture element unit including a picture element electrode formed in connection with the source electrode of the thin film transistor unit; and a storage capacitance unit connected to the picture element electrode of the picture element unit, the storage capacitance unit including a storage capacitance electrode formed on the transparent insulating substrate and formed of a metal layer of the same material as the gate electrode; a dielectric film formed on the storage capacitance electrode and formed of an insulating film common with the gate insulating film and a non-doped semiconductor layer of the same material as the semiconductor active layer; and a counter electrode formed on the dielectric film and formed of a doped semiconductor layer of the same material as the semiconductor contact layer and a metal layer of the same material as the source electrode and the drain electrode, the counter electrode being connected to the picture element electrode.
Claim 3
Dependent Claim
35 words
A thin film transistor matrix device according to claim 1, wherein the counter electrode is connected to the picture element electrode through a contact hole opened in a protecting film common with the passivation film.
Claim 4
Dependent Claim
21 words
A thin film transistor matrix device according to claim 1, wherein the semiconductor active layer is an amorphous silicon active layer.
Claim 5
Dependent Claim
253 words
A thin film transistor matrix device comprising: a transparent insulating substrate; a thin film transistor unit including a gate electrode formed on the transparent insulating substrate; a semiconductor active layer formed on the gate electrode through a gate insulating film; a source electrode and a drain electrode formed opposed to each other on the semiconductor active layer through a semiconductor contact layer; and a protecting film covering the source electrode and the drain electrode; a picture element unit including a picture element electrode formed in connection with the source electrode of the thin film transistor unit; a storage capacitance, unit connected to the picture dement electrode of the picture element unit; a gate terminal unit connected to the gate electrode of the thin film transistor unit through a gate bus line; and a drain terminal unit connected to the drain electrode of the thin film transistor unit through a drain bus line, the gate terminal unit including a gate terminal lower electrode formed on the transparent insulating substrate and formed of a metal layer common with the gate electrode; and a gate terminal upper electrode formed on the gate terminal lower electrode through a contact hole in an insulating film common with the gate insulating film and a contact hole in the protecting film the gate terminal upper electrode being formed of a transparent conducting film of the same material as the picture element electrode, the contact hole in the insulating film and the contact hole in the protecting film being substantially aligned.
Claim 6
Dependent Claim
253 words
A thin film transistor matrix device comprising: a transparent insulating substrate; a thin film transistor unit including a gate electrode formed on the transparent insulating substrate; a semiconductor active layer formed on the gate electrode through a gate insulating film; a source electrode and a drain electrode formed opposed to each other on the semiconductor active layer through a semiconductor contact layer; and a protecting film covering the source electrode and the drain electrode; a picture element unit including a picture element electrode formed in connection with the source electrode of the thin film transistor unit; a storage capacitance, unit connected to the picture dement electrode of the picture element unit; a gate terminal unit connected to the gate electrode of the thin film transistor unit through a gate bus line; and a drain terminal unit connected to the drain electrode of the thin film transistor unit through a drain bus line, the gate terminal unit including a gate terminal lower electrode formed on the transparent insulating substrate and formed of a metal layer common with the gate electrode; and a gate terminal upper electrode formed on the gate terminal lower electrode through a contact hole in an insulating film common with the gate insulating film and a contact hole in the protecting film the gate terminal upper electrode being formed of a transparent conducting film of the same material as the picture element electrode, the contact hole in the insulating film and the contact hole in the protecting film being substantially aligned.
Claim 7
Dependent Claim
21 words
A thin film transistor matrix device according to claim 4, wherein the semiconductor active layer is an amorphous silicon active layer.
Claim 8
Dependent Claim
268 words
A thin film transistor matrix device comprising: a transparent insulating substrate; a thin film transistor unit including a gate electrode formed on the transparent insulating substrate; a semiconductor active layer formed on the gate electrode through a gate insulating film; a source electrode and a drain electrode formed opposed to each other on the semiconductor active layer through a semiconductor contact layer; and a protecting film covering the source electrode and the drain electrode; a picture element unit including a picture element electrode formed in connection with the source electrode of the thin film transistor unit; a storage capacitance unit connected to the picture element electrode of the picture element unit; a gate terminal unit connected to the gate electrode of the thin film transistor unit through a gate bus line; and a drain terminal unit connected to the drain electrode of the thin film transistor unit through a drain bus line, the gate terminal unit including a gate terminal lower electrode formed on the transparent insulating substrate arid formed of a metal layer common with the gate electrode; and a gate terminal upper electrode formed on the gate terminal lower electrode through a contact hole in an insulating film common with the gate insulating film and a contact hole in the protecting film, the gate terminal upper electrode being formed of a transparent conducting film of the same material as the picture element electrode, the protecting film and the insulating film being in contact in the vicinity of the contact hole in the insulating film and in the vicinity of the contact hole in the protecting film.
Claim 9
Dependent Claim
268 words
A thin film transistor matrix device comprising: a transparent insulating substrate; a thin film transistor unit including a gate electrode formed on the transparent insulating substrate; a semiconductor active layer formed on the gate electrode through a gate insulating film; a source electrode and a drain electrode formed opposed to each other on the semiconductor active layer through a semiconductor contact layer; and a protecting film covering the source electrode and the drain electrode; a picture element unit including a picture element electrode formed in connection with the source electrode of the thin film transistor unit; a storage capacitance unit connected to the picture element electrode of the picture element unit; a gate terminal unit connected to the gate electrode of the thin film transistor unit through a gate bus line; and a drain terminal unit connected to the drain electrode of the thin film transistor unit through a drain bus line, the gate terminal unit including a gate terminal lower electrode formed on the transparent insulating substrate arid formed of a metal layer common with the gate electrode; and a gate terminal upper electrode formed on the gate terminal lower electrode through a contact hole in an insulating film common with the gate insulating film and a contact hole in the protecting film, the gate terminal upper electrode being formed of a transparent conducting film of the same material as the picture element electrode, the protecting film and the insulating film being in contact in the vicinity of the contact hole in the insulating film and in the vicinity of the contact hole in the protecting film.
References Cited (Backward Citations)
JPS58190063A
Cited
JPS6197864A
Cited
JPS6273659A
Cited
JPH01124824A
Cited
JPH0248639A
Cited
JPH03274029A
Cited
JPH04265945A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-01-08 | 1999-07-10 | 2000-01-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-01-08 | 2003-07-10 | 2004-01-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-01-08 | 2007-07-10 | 2008-01-09 | $7700.00 | Window Closed / Lapsed |