US5481727A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Bus control for a plurality of digital signal processors connected to a common memory
Assignee: Mitsubishi Electric Corp
•
Filing: 1993-11-15
•
Granted: 1996-01-02
•
Expires: 2013-11-15
Abstract
Abstract A multiprocessor type time varying image encoding system having a plurality of digital signal processor (DSP) modules (DMM's) connected in parallel, each DMM having a DSP, a local memory and an interrupt control unit, a plurality of common memories for storing data which is being processed, parameters, etc., an input frame memory which enables reading and writing operations to be executed asynchronously, a combination of a task control unit and a task table for distributing tasks to the DMM's, a plurality of independent common buses, and a combination of a bus control unit and a bus control table for bus sharing control.
Inventors
- 👤 Kenichi Asano
- 👤 Ryuta Suzuki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 15:30
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; H; H04; H04N; H04N19/00; H04N19/90; H04N19/98; G06T; G06T1/00; G06T1/20
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
208 words
An image encoding system with bus control, the system comprising: a common memory; a plurality of unit processors, each of the unit processors including: means for receiving input data, means for processing input data, means for outputting processed data, and means for requesting access to the common memory a predetermined time before processing being executed by the processing means is completed, wherein the means for requesting access to the common memory includes: means for controlling the means for processing input data to pause processing the predetermined time before processing being executed by the processing means is completed; means, responsive to the means for controlling, for outputting a transfer request to the arbitration means: and means, responsive to the means for outputting a transfer request, for controlling the means for processing input data to resume processing; and arbitration means including: means for determining priority among requests by the requesting means, means for granting access to the common memory to a requesting unit processor if no other unit processor has requested access to the common memory, and means for granting access to one of the unit processors in order of priority determined by the means for determining if more than one unit processor has requested access to the common memory.
Claim 2
Dependent Claim
208 words
An image encoding system with bus control, the system comprising: a common memory; a plurality of unit processors, each of the unit processors including: means for receiving input data, means for processing input data, means for outputting processed data, and means for requesting access to the common memory a predetermined time before processing being executed by the processing means is completed, wherein the means for requesting access to the common memory includes: means for controlling the means for processing input data to pause processing the predetermined time before processing being executed by the processing means is completed; means, responsive to the means for controlling, for outputting a transfer request to the arbitration means: and means, responsive to the means for outputting a transfer request, for controlling the means for processing input data to resume processing; and arbitration means including: means for determining priority among requests by the requesting means, means for granting access to the common memory to a requesting unit processor if no other unit processor has requested access to the common memory, and means for granting access to one of the unit processors in order of priority determined by the means for determining if more than one unit processor has requested access to the common memory.
Claim 3
Dependent Claim
60 words
The system of claim 1 wherein each unit processor further includes: an instruction memory for alternately storing a data transfer instruction for transferring one of the input data and the processed data, and a processing instruction for processing data, wherein the means for requesting access requests access to execute the data transfer instruction prior to completing a preceding processing task.
Claim 4
Dependent Claim
14 words
The system of claim 1 wherein the plurality of processors are arranged in parallel.
Claim 5
Dependent Claim
34 words
The system of claim 1 wherein the processors are connected in series for pipeline processing, the system further comprising a number of two-port memories, each of which is interposed between pairs of adjacent processors.
Claim 6
Dependent Claim
176 words
A bus control method for a system in which a plurality of digital signal processors are coupled to a common memory which can be accessed by two or more processors in a time-division manner, said method comprising the steps of: requesting access, by one of the processors, to a common memory a predetermined time before the completion of the processing presently being executed thereby; wherein the step of requesting access includes: controlling the processors to pause processing the predetermined time before the completion of the processing presently being executed; outputting a transfer request to an arbitration means; and controlling the processors to resume processing in response to the transfer request; determining, by a means for determining, whether two or more of said processors simultaneously request access to a common memory; granting access to said one processor in response to a determination that no other processor has requested access; and granting common memory access to one of the processors in order of priority, in response to a determination that two or more processors have simultaneously requested access.
Claim 7
Dependent Claim
176 words
A bus control method for a system in which a plurality of digital signal processors are coupled to a common memory which can be accessed by two or more processors in a time-division manner, said method comprising the steps of: requesting access, by one of the processors, to a common memory a predetermined time before the completion of the processing presently being executed thereby; wherein the step of requesting access includes: controlling the processors to pause processing the predetermined time before the completion of the processing presently being executed; outputting a transfer request to an arbitration means; and controlling the processors to resume processing in response to the transfer request; determining, by a means for determining, whether two or more of said processors simultaneously request access to a common memory; granting access to said one processor in response to a determination that no other processor has requested access; and granting common memory access to one of the processors in order of priority, in response to a determination that two or more processors have simultaneously requested access.
References Cited (Backward Citations)
US4257095A
Cited
US4320457A
Cited
US4320467A
Cited
US4419724A
Cited
US4453214A
Cited
US4458314A
Cited
US4620278A
Cited
US4627018A
Cited
US4626843A
Cited
US4633394A
Cited
US4752872A
Cited
US4818985A
Cited
US5142682A
Cited
US4837682A
Cited
US5073871A
Cited
US5396603A
Cited
US5129090A
Cited
US5193194A
Cited
US5179709A
Cited
US5088024A
Cited
US5121487A
Cited
US5127089A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-01-01 | 1999-07-03 | 2000-01-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-01-01 | 2003-07-03 | 2004-01-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-01-01 | 2007-07-03 | 2008-01-02 | $7700.00 | Window Closed / Lapsed |