US5481697A
Expired / Lapsed
US
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An apparatus for providing a clock signal for a microprocessor at a selectable one of a plurality of frequencies and for dynamically switching between any of said plurality of frequencies
Assignee: Intel Corp
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Filing: 1994-09-30
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Granted: 1996-01-02
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Expires: 2014-09-30
Abstract
Abstract A variable frequency clock generator provides complementary phase clock signals for a microprocessor at a selectable one of a plurality of frequencies. The outputs may be dynamically switched between any of the frequencies so that every cycle of the phase clock signals has a duration at least as great as the cycle duration of the highest frequency.
Inventors
- 👤 Gregory Mathews
- 👤 Edward Zager
- 👤 Sundari Mitra
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 21:01
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/15; H03K5/15013; H03K5/1506; H03K5/15066; G; G06; G06F; G06F1/00; G06F1/04; G06F1/08; H03L; H03L7/00; H03L7/06; H03L7/16
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
229 words
An apparatus for providing a cyclic CPU clock signal for a microprocessor at a selectable one of a plurality of frequencies and for dynamically switching between any of said plurality of frequencies, wherein said apparatus comprises: a) means for receiving a master clock signal; b) control interface means for generating a clock set signal synchronous with said master clock signal; c) clock divider means, operatively coupled to said master clock signal and said control interface means to receive said clock set signal, for generating a plurality of clock signals, each at a respective one of said plurality of frequencies that are submultiples of the master clock signal, said clock divider means including means responsive to said clock set signal for forcing all of said plurality of clock signals to a common state and to thereupon restart in said common state synchronous with said master clock signal; d) multiplexing means operatively coupled to said clock divider means for selecting as said CPU clock signal one of said plurality of clock signals after said plurality of clock signals are restarted such that Said CPU clock signal is dynamically switched between said plurality of frequencies in synchronism with said master clock signal and such that every cycle of said CPU clock signal has a cycle duration at least as great as the cycle duration of a highest of said plurality of frequencies.
Claim 2
Independent Claim
229 words
An apparatus for providing a cyclic CPU clock signal for a microprocessor at a selectable one of a plurality of frequencies and for dynamically switching between any of said plurality of frequencies, wherein said apparatus comprises: a) means for receiving a master clock signal; b) control interface means for generating a clock set signal synchronous with said master clock signal; c) clock divider means, operatively coupled to said master clock signal and said control interface means to receive said clock set signal, for generating a plurality of clock signals, each at a respective one of said plurality of frequencies that are submultiples of the master clock signal, said clock divider means including means responsive to said clock set signal for forcing all of said plurality of clock signals to a common state and to thereupon restart in said common state synchronous with said master clock signal; d) multiplexing means operatively coupled to said clock divider means for selecting as said CPU clock signal one of said plurality of clock signals after said plurality of clock signals are restarted such that Said CPU clock signal is dynamically switched between said plurality of frequencies in synchronism with said master clock signal and such that every cycle of said CPU clock signal has a cycle duration at least as great as the cycle duration of a highest of said plurality of frequencies.
Claim 3
Dependent Claim
39 words
The apparatus of claim 1 wherein said control interface means includes clock inhibit means responsive to a clock stop signal for causing said clock set signal to be held in a logic state that stops said CPU clock signal.
Claim 4
Dependent Claim
38 words
The apparatus of claim 1 wherein said cyclic CPU clock signal is a first CPU clock signal and further comprising means for generating a second CPU clock signal that is a complement of the first CPU clock signal.
Claim 5
Independent Claim
190 words
A method of providing a cyclic CPU clock signal for a microprocessor at a selectable one of a plurality of frequencies and for dynamically switching between any of said plurality of frequencies, wherein said method comprises the steps of: a) receiving a master clock signal; b) generating a clock set signal synchronous with said master clock signal; c) generating a plurality of clock signals at said plurality of frequencies that are submultiples of said master clock signal; d) forcing all of said plurality of clock signals to a common state in response to said clock set signal and concurrently restarting all of said plurality of clock signals in said common state synchronous with said master clock signal; e) selecting as said CPU clock signal one of said plurality of clock signals after said plurality of clock signals are restarted such that said CPU clock signal is dynamically switched between said plurality of frequencies in synchronism with said master clock signal and such that every cycle of said CPU clock signal has a cycle duration at least as great as the cycle duration of a highest of said plurality of frequencies.
Claim 6
Independent Claim
190 words
A method of providing a cyclic CPU clock signal for a microprocessor at a selectable one of a plurality of frequencies and for dynamically switching between any of said plurality of frequencies, wherein said method comprises the steps of: a) receiving a master clock signal; b) generating a clock set signal synchronous with said master clock signal; c) generating a plurality of clock signals at said plurality of frequencies that are submultiples of said master clock signal; d) forcing all of said plurality of clock signals to a common state in response to said clock set signal and concurrently restarting all of said plurality of clock signals in said common state synchronous with said master clock signal; e) selecting as said CPU clock signal one of said plurality of clock signals after said plurality of clock signals are restarted such that said CPU clock signal is dynamically switched between said plurality of frequencies in synchronism with said master clock signal and such that every cycle of said CPU clock signal has a cycle duration at least as great as the cycle duration of a highest of said plurality of frequencies.
Claim 7
Dependent Claim
38 words
The method of claim 4 wherein said cyclic CPU clock signal is a first CPU clock signal and further comprising means for generating a second CPU clock Signal that is a complement of the first CPU clock signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-01-01 | 1999-07-03 | 2000-01-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-01-01 | 2003-07-03 | 2004-01-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-01-01 | 2007-07-03 | 2008-01-02 | $7700.00 | Window Closed / Lapsed |