Patent US5481677A successfully refreshed from Google Patents.
US5481677A
Expired / Lapsed
US
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Data transfer system in which data is transferred to or from a data memory during an instruction fetch cycle
Assignee: Oki Electric Industry Co Ltd
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Filing: 1992-09-03
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Granted: 1996-01-02
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Expires: 2012-09-03
Abstract
Abstract A data transfer system has an address bus and a data bus, each divided into two parts by a bus switch. A microprocessor and program memory are connected to the first parts of the address and data buses. A data memory, data transfer controller, and input/output devices are connected to the second parts of tile address and data buses. While the microprocessor is fetching an instruction from the program memory, the bus switches disconnect the two parts of the buses, enabling the data transfer controller to transfer data directly between the data memory and input/output devices. At other times the bus switches connect the two parts of the buses, enabling the microprocessor to access the data memory and Input/output devices.
Inventors
- 👤 Yoshihide Kai
- 👤 Hiroya Tanigawa
- 👤 Toshihiko Wakahara
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 15:38
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/20; G06F13/28
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
344 words
A data transfer system, comprising: an address bus means, having a first part and a second part, for transferring address information; a data bus means, having a first part and a second part, for transferring data; a control bus means for transferring control signals; a yon-Neumann-type microprocessor connected to said first part of said address bus means, said first part of said data bus means, and said control bus means; a program memory means, connected to said first part of said address bus means, said first part of said data bus means, and said control bus means, for storing instructions to be executed by said microprocessor during instruction cycles; a data memory means, connected to said second part of said address bus means, said second part of said data bus means, and said control bus means, for storing data; at least one I/O device connected to said second part of said data bus means and said control bus means; an address bus switch means for disconnecting said first part of said address bus means from said second part of said address bus means when said microprocessor is fetching an instruction from said program memory means, and connecting said first part of said address bus means to said second part of said address bus means at other times in each instruction cycle; a data bus switch means for disconnecting said first part of said data bus means from said second part of said data bus means when said microprocessor is fetching an instruction from said program memory means, and connecting said first part of said data bus means to said second part of said data bus means at said other times; and data transfer controller means, connected to said second part of said address bus means and said control bus means, for generating addresses and control signals to perform direct transfers of data between said data memory means and said at least one I/O device via said second part of said data bus means while said microprocessor is fetching instructions from said program memory means.
Claim 2
Dependent Claim
344 words
A data transfer system, comprising: an address bus means, having a first part and a second part, for transferring address information; a data bus means, having a first part and a second part, for transferring data; a control bus means for transferring control signals; a yon-Neumann-type microprocessor connected to said first part of said address bus means, said first part of said data bus means, and said control bus means; a program memory means, connected to said first part of said address bus means, said first part of said data bus means, and said control bus means, for storing instructions to be executed by said microprocessor during instruction cycles; a data memory means, connected to said second part of said address bus means, said second part of said data bus means, and said control bus means, for storing data; at least one I/O device connected to said second part of said data bus means and said control bus means; an address bus switch means for disconnecting said first part of said address bus means from said second part of said address bus means when said microprocessor is fetching an instruction from said program memory means, and connecting said first part of said address bus means to said second part of said address bus means at other times in each instruction cycle; a data bus switch means for disconnecting said first part of said data bus means from said second part of said data bus means when said microprocessor is fetching an instruction from said program memory means, and connecting said first part of said data bus means to said second part of said data bus means at said other times; and data transfer controller means, connected to said second part of said address bus means and said control bus means, for generating addresses and control signals to perform direct transfers of data between said data memory means and said at least one I/O device via said second part of said data bus means while said microprocessor is fetching instructions from said program memory means.
Claim 3
Dependent Claim
17 words
The system of claim 1, wherein said other times includes times when said microprocessor is executing instructions.
Claim 4
Dependent Claim
95 words
The system of claim 1, wherein: said microprocessor executes a program during a sequence of instructions cycles, each instruction cycle including an instruction fetch portion and an instruction executing portion; said address bus switch means disconnects said first part of said address bus means from said second part of said address bus means during said instruction fetch portion of an instruction cycle; and said data bus switch means disconnects said first part of said data bus means from said second part of said data bus means during said instruction fetch portion of an instruction cycle.
Claim 5
Dependent Claim
33 words
The system of claim 3, wherein said instruction executing portion of an instruction cycle may be employed by said microprocessor for accessing said data memory means or said at least one I/O device.
Claim 6
Dependent Claim
78 words
The system of claim 1, wherein said second part of said address bus means comprises a third part to which said data memory means is connected, and a fourth part to which said at least one I/O device is connected, and further comprising a secondary address bus switch means for connecting and disconnecting said third part and said fourth part, said secondary address bus switch means being switched on and off simultaneously with said address bus switch means.
Claim 7
Dependent Claim
170 words
The system of claim 5, wherein said data transfer controller means comprises: a data memory address generator means for supplying data memory addresses to said third part of said address bus means when said secondary address bus switch means is switched off; a data memory timing generator means for sending control signals to said data memory means; an I/O address generator means for supplying I/O addresses to said fourth part of said address bus means; an I/O timing generator means for sending control signals to said at least one I/O device; and a control circuit means, connected to said control bus means, said second part of said data bus means, said data memory address generator means, said data memory timing generator means, said I/O address generator means, and said I/O timing generator means, for initializing said data memory address generator means, said data memory timing generator means, said I/O address generator means, and said I/O timing generator means according to information received from said microprocessor via said data bus means.
Claim 8
Dependent Claim
73 words
The system of claim 6, further comprising control signal switches, switched simultaneously with said address bus switch means and data bus switch means, for selecting either control signals received from said microprocessor via said control bus means or control signals received directly from said data memory timing generator means and said I/O timing generator means and providing the signals thus selected to said data memory means and said at least one I/O device.
Claim 9
Dependent Claim
38 words
The system of claim 1, wherein said microprocessor sends said data transfer controller means an Instruction Fetch signal that Is active when said microprocessor is fetching an instruction from said program memory means and inactive at other times.
Claim 10
Dependent Claim
31 words
The system of claim 8, wherein said data transfer controller means is responsive to said Instruction Fetch signal for controlling said address bus switch means and said data bus switch means.
Claim 11
Dependent Claim
129 words
The system of claim 9, wherein said data bus transfer controller means causes said address bus switch means to disconnect said first part of said address bus means from said second part of said address bus means and causes said data bus switch means to disconnect said first part of said data bus means from said second part of said data bus means when said Instruction Fetch signal is active, and causes said address bus switch means to connect said first part of said address bus means to said second part of said address bus means and causes said data bus switch means to connect said first part of said data bus means to said second part of said data bus means when said Instruction Fetch signal is inactive.
Claim 12
Dependent Claim
32 words
The system of claim 10, wherein when said microprocessor activates said Instruction Fetch signal when it begins fetching an instruction, and deactivates said Instruction Fetch signal when it finishes fetching the instruction.
Claim 13
Dependent Claim
113 words
The system of claim 8, wherein said data transfer controller means comprises: an address register means for storing pairs of addresses, each comprising a data memory address and an I/O address; an index counter means for cyclically indicating successive pairs of addresses in said address register means; a gate circuit means for providing the data memory address indicated by said index counter means to said second part of said address bus means while said microprocessor is fetching an instruction from said program memory means; and an I/O address decoder means for decoding the I/O address indicated by said index counter means and generating control signals to select said at least one I/O device.
Claim 14
Dependent Claim
24 words
The system of claim 12, wherein said index counter means increments once each time said microprocessor fetches an instruction from said program memory means.
Claim 15
Dependent Claim
26 words
The system of claim 12, wherein said address register means also stores, for each of said pairs of addresses, a flag indicating a data transfer direction.
Claim 16
Dependent Claim
36 words
The system of claim 14, wherein said data transfer controller means further comprises means for generating a data memory read signal or a data memory write signal according to said Instruction Fetch signal and said flag.
Claim 17
Dependent Claim
336 words
A data transfer system, comprising: an address bus means, having a first part and a second part, for transferring address information; a data bus means, having a first part and a second part, for transferring data; a control bus means for transferring control signals; a von-Neumann-type microprocessor connected to said first part of said address bus means, said first part of said data bus means, and said control bus means; a program memory means, connected to said first part of said address bus means, said first part of said data bus means, and said control bus means, for storing instructions to be executed by said microprocessor; a data memory means, connected to said second part of said address bus means, said second part of said data bus means, and said control bus means, for storing data; at least one I/O device connected to said second part of said data bus means and said control bus means; an address bus switch means for disconnecting said first part of said address bus means from said second part of said address bus means every time said microprocessor fetches an instruction from said program memory means, and connecting said first part of said address bus means to said second part of said address bus means at other times; a data bus switch means for disconnecting said first part of said data bus means from said second part of said data bus means every time said microprocessor fetches an instruction from said program memory means, and connecting said first part of said data bus means to second part of said data bus means at said other times; and data transfer controller means, connected to said second part of said address bus means and said control bus means, for generating addresses and control signals to perform direct transfers of data between said data memory means and said at least one I/O device via said second part of said data bus means while said microprocessor is fetching instructions from said program memory means.
Claim 18
Dependent Claim
336 words
A data transfer system, comprising: an address bus means, having a first part and a second part, for transferring address information; a data bus means, having a first part and a second part, for transferring data; a control bus means for transferring control signals; a von-Neumann-type microprocessor connected to said first part of said address bus means, said first part of said data bus means, and said control bus means; a program memory means, connected to said first part of said address bus means, said first part of said data bus means, and said control bus means, for storing instructions to be executed by said microprocessor; a data memory means, connected to said second part of said address bus means, said second part of said data bus means, and said control bus means, for storing data; at least one I/O device connected to said second part of said data bus means and said control bus means; an address bus switch means for disconnecting said first part of said address bus means from said second part of said address bus means every time said microprocessor fetches an instruction from said program memory means, and connecting said first part of said address bus means to said second part of said address bus means at other times; a data bus switch means for disconnecting said first part of said data bus means from said second part of said data bus means every time said microprocessor fetches an instruction from said program memory means, and connecting said first part of said data bus means to second part of said data bus means at said other times; and data transfer controller means, connected to said second part of said address bus means and said control bus means, for generating addresses and control signals to perform direct transfers of data between said data memory means and said at least one I/O device via said second part of said data bus means while said microprocessor is fetching instructions from said program memory means.
References Cited (Backward Citations)
US4455620A
Cited
US4847750A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-01-01 | 1999-07-03 | 2000-01-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-01-01 | 2003-07-03 | 2004-01-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-01-01 | 2007-07-03 | 2008-01-02 | $7700.00 | Window Closed / Lapsed |