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US5481646A Expired / Lapsed US ⏱️ 0.0 years remaining

Neuron unit and neuron unit network

Assignee: Ricoh Co Ltd
•
Filing: 1994-04-22
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Granted: 1996-01-02
•
Expires: 2014-04-22
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Abstract

Abstract A neuron unit simultaneously processes a plurality of binary input signals. The neuron unit includes input lines for receiving first and second input signals which undergo transitions with time, first and second memories for storing weighting coefficients, a first gate for successively obtaining a logical product of one of the first input signals and a corresponding one of the weighting coefficients read out from the first memory for each of the first input signals, a second gate for successively obtaining a logical product of one of the second input signals and a corresponding one of the weighting coefficients read out from the second memory for each of the second input signals, a third gate for obtaining a logical sum of logical products output from the first gate, a fourth gate for obtaining a logical sum of logical products output from the second gate, and an output part including an inverter for inverting the logical sum output from the fourth gate and a gate for obtaining one of a logical product and a logical sum of the logical sum output from the third gate and an inverted logical sum output from the inverter. This gate outputs an output signal of the neuron unit.

Inventors

  • 👤 Toshiyuki Furuta
  • 👤 Hiroyuki Horiguchi
  • 👤 Hirotoshi Eguchi

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-06 00:09
CPC Classifications
G; G06; G06N; G06N3/00; G06N3/02; G06N3/06; G06N3/063

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 215 words
A neuron unit for processing a plurality of binary input signals and for outputting a neuron output signal which is indicative of a result of the processing, said neuron unit comprising: a) a plurality of first gate means for carrying out respective synchronous logical operations on a binary input signal using a synchronizing clock signal, the carrying out of the respective synchronous logical operations using weighting coefficients which are each represented by a pulse density which is defined by at least one of first and second values which are arranged at random: i) a number of the first values corresponding to a high binary signal level; and ii) a number of the second values corresponding to a low binary signal level; within a predetermined time; b) a second gate means, coupled to said first gate means, for carrying out a logical operation on an excitatory output signal of each of said first gate means; c) a third gate means, coupled to said first gate means, for carrying out a logic operation on an inhibitory output signal for each of said first gate means; and d) a fourth gate means, coupled to said second and third gate means, for synthesizing output signals of said second and third gate means and for outputting the neuron output signal.
Claim 2
Dependent Claim 215 words
A neuron unit for processing a plurality of binary input signals and for outputting a neuron output signal which is indicative of a result of the processing, said neuron unit comprising: a) a plurality of first gate means for carrying out respective synchronous logical operations on a binary input signal using a synchronizing clock signal, the carrying out of the respective synchronous logical operations using weighting coefficients which are each represented by a pulse density which is defined by at least one of first and second values which are arranged at random: i) a number of the first values corresponding to a high binary signal level; and ii) a number of the second values corresponding to a low binary signal level; within a predetermined time; b) a second gate means, coupled to said first gate means, for carrying out a logical operation on an excitatory output signal of each of said first gate means; c) a third gate means, coupled to said first gate means, for carrying out a logic operation on an inhibitory output signal for each of said first gate means; and d) a fourth gate means, coupled to said second and third gate means, for synthesizing output signals of said second and third gate means and for outputting the neuron output signal.
Claim 3
Dependent Claim 33 words
The neuron unit as claimed in claim 1, further comprising: memory means, coupled to said first gate means, for storing the weighting coefficients which are supplied to each of said first gate means.
Claim 4
Dependent Claim 20 words
The neuron unit as claimed in claim 2, wherein said memory means stores the weighting coefficients as the pulse density.
Claim 5
Dependent Claim 24 words
The neuron unit as claimed in claim 1, wherein each of the binary input signals also describe a signal quantity as the pulse density.
Claim 6
Dependent Claim 58 words
The neuron unit as claimed in claim 1, wherein: said first gate means are grouped into an excitatory group and an inhibitory group; said second gate means is coupled to each of the first gate means forming the excitatory group; and said third gate means is coupled to each of the first gate means forming the inhibitory group.

References Cited (Backward Citations)

US5058184A Cited
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JPH01244567A Cited
US4943931A Cited
US4893255A Cited
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US4950917A Cited
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USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1999-01-01 1999-07-03 2000-01-02 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2003-01-01 2003-07-03 2004-01-02 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2007-01-01 2007-07-03 2008-01-02 $7700.00 Window Closed / Lapsed

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