Digital artificial neural processor

Claim 1

In an artificial neural system containing a plurality of neural processors and means for generating digital numbers and flag bits, the improvement in which said neural processors each comprise: a plurality of number receiving inputs for receiving numbers in binary form and a corresponding plurality of flag bit inputs for receiving flag bits, each of said number receiving inputs being associated with one of said flag bit inputs to permit a flat bit to be applied prior to supply of a number to the associated number input; a feedback signal input; a number output; a flag bit output; a plurality of pairs of registers forming register pairs, each said pair including a primary register for receiving and storing numbers inputted in binary form to an associated number input of the neural processor, and a buffer register; each of said primary registers in said plurality having first and second register inputs and an output with said primary register storing the number last applied in time at either of said first or second register input; said number receiving inputs being connected to an input of an associated one of said primary registers for applying a number appearing at the respective input to the associated primary register; each said buffer register of said pairs of registers having first, second and third buffer register inputs and an output, said buffer register being responsive to a flag bit at one input for conditioning said buffer register to receive a new number, and being responsive to the binary number stored in the primary register in said register pair for also receiving and storing a copy of the binary number stored in the associated primary register, and said buffer register further being responsive to signals of a first and second kind, respectively, applied at the feedback input for incrementing and decrementing, respectively, the number stored in said buffer register; first means coupling the output of each buffer register to the second input of the associated primary register for setting the number stored in said primary register to the value of the number in said associated buffer register; second means coupling said output of said primary register in each pair to the first input of the associated buffer register; third means for connecting the third input of each said buffer registers to said feedback signal input to provide to said third input externally applied feedback signals, said feedback signals being of either a first and second kind to increment and decrement, respectively, said buffer registers; fourth means responsive to a flag bit at any of said flag bit inputs for providing a flag bit at said flag bit output of the neural processor; fifth means for providing at said number output a number representing the average of the numbers stored in all said buffer registers of said register pairs.