US3613084A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Trainable digital apparatus
Assignee: AT&T Inc
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Filing: 1968-09-24
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Granted: 1971-10-12
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Expires: 1988-09-24
Abstract
Abstract A plurality of all-digital elements are interconnected to form an n-input single-output network that can be structurally organized during a training or learning period to implement specified logical functions of n variables. Actually, for up to about 10 input variables, any desired Boolean function may be implemented by training a single element. For larger numbers of input variables, a wide class of functions may be implemented by training a multielement network. During training (for an array that contains either a single element or a plurality of interconnected elements) the response of the array is monitored and compared with the desired response for each of a set of input signals. As a result of each comparison operation, identical binary training signals are simultaneously applied to every element of the array. These signals may cause the internal states of the element(s) to change. By systematically changing these individual states in accordance with prescribed training strategies, the overall array is ultimately configured to give correct responses to at least specified portion of subsequentlyapplied input signals.
Inventors
- 👤 William W Armstrong
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 13:40
CPC Classifications
G; G06; G06N; G06N3/00; G06N3/02; G06N3/06; G06N3/063
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
299 words
An m-input single-output trainable element comprising: means for simultaneously supplying m binary input signals, where m is a positive integer greater than 1, input logic means, including 2m output leads, responsive to said input signals for providing a unique binary signal on a different one of said leads in respective response to each different one of the 2m different possible combinations of said input signals, 2m controller means each including a distinct state-indicative signal output lead and each being connected to a different one of said 2m output leads of said input logic means, each of said controller means being characterized by a plurality of stable states and being enabled by a unique binary signal being applied thereto from said input logic means to receive training signals, at least some of said training signals being adapted to change the state of said controller means, means for applying training signals to said controller meanS, and output logic means, including a single output lead, responsive to signals appearing on said state-indicative output leads and to signals appearing on the output leads of said input logic means for applying to said single output lead a signal that is a specified function of said m input signals, wherein each of said controller means comprises reversible counter means and means adapted to be enabled by a unique binary signal applied to said controller means from said input logic means for routing training signals to said counter means, wherein each of said controller means further includes a bistable unit, and wherein said routing means includes circuitry responsive to said reversible counter means being in a predetermined condition and to the receipt of training signals of a specified type for applying a resetting signal to said counter means and a complementing signal to said bistable unit.
Claim 2
Dependent Claim
299 words
An m-input single-output trainable element comprising: means for simultaneously supplying m binary input signals, where m is a positive integer greater than 1, input logic means, including 2m output leads, responsive to said input signals for providing a unique binary signal on a different one of said leads in respective response to each different one of the 2m different possible combinations of said input signals, 2m controller means each including a distinct state-indicative signal output lead and each being connected to a different one of said 2m output leads of said input logic means, each of said controller means being characterized by a plurality of stable states and being enabled by a unique binary signal being applied thereto from said input logic means to receive training signals, at least some of said training signals being adapted to change the state of said controller means, means for applying training signals to said controller meanS, and output logic means, including a single output lead, responsive to signals appearing on said state-indicative output leads and to signals appearing on the output leads of said input logic means for applying to said single output lead a signal that is a specified function of said m input signals, wherein each of said controller means comprises reversible counter means and means adapted to be enabled by a unique binary signal applied to said controller means from said input logic means for routing training signals to said counter means, wherein each of said controller means further includes a bistable unit, and wherein said routing means includes circuitry responsive to said reversible counter means being in a predetermined condition and to the receipt of training signals of a specified type for applying a resetting signal to said counter means and a complementing signal to said bistable unit.
Claim 3
Dependent Claim
327 words
A trainable logical network comprising a plurality of m-input single-output trainable elements, each of said elements comprising: means for simultaneously supplying m binary input signals, where m is a positive integer greater than 1, input logic means, including 2m output leads, responsive to said input signals for providing a unique binary signal on a different one of said leads in respective response to each different one of the 2m different possible combinations of said input signals, 2m controller means each including a distinct state-indicative signal output lead and each being connected to a different one of said 2m output leads of said input logic means, each of said controller means being characterized by a plurality of stable states and being enabled by a unique binary signal being applied thereto from said input logic means to receive training signals, at least some of said training signals being adapted to change the state of said controller means, means for applying training signals to said controller means, and output logic means, including a single output lead, responsive to signals appearing on said state-indicative output leads and to signals appearing on the output leads of said input logic means for applying to said single output lead a signal that is a specified function of said m input signals, wherein each of said controller means comprises reversible counter means and means adapted to be enabled by a unique binary signal applied to said controller means from said input logic means for routing training signals to said counter means, wherein each of said controller means further includes a bistable unit, and wherein said routing means including circuitry responsive to said reversible counter means being in a predetermined condition and to the receipt of training signals of a specified type for applying a resetting signal to said counter means and a complementing signal to said bistable unit, and means interconnecting said plurality of elements in a loop-free configuration to form a multiple-input single-output array.
Claim 4
Dependent Claim
327 words
A trainable logical network comprising a plurality of m-input single-output trainable elements, each of said elements comprising: means for simultaneously supplying m binary input signals, where m is a positive integer greater than 1, input logic means, including 2m output leads, responsive to said input signals for providing a unique binary signal on a different one of said leads in respective response to each different one of the 2m different possible combinations of said input signals, 2m controller means each including a distinct state-indicative signal output lead and each being connected to a different one of said 2m output leads of said input logic means, each of said controller means being characterized by a plurality of stable states and being enabled by a unique binary signal being applied thereto from said input logic means to receive training signals, at least some of said training signals being adapted to change the state of said controller means, means for applying training signals to said controller means, and output logic means, including a single output lead, responsive to signals appearing on said state-indicative output leads and to signals appearing on the output leads of said input logic means for applying to said single output lead a signal that is a specified function of said m input signals, wherein each of said controller means comprises reversible counter means and means adapted to be enabled by a unique binary signal applied to said controller means from said input logic means for routing training signals to said counter means, wherein each of said controller means further includes a bistable unit, and wherein said routing means including circuitry responsive to said reversible counter means being in a predetermined condition and to the receipt of training signals of a specified type for applying a resetting signal to said counter means and a complementing signal to said bistable unit, and means interconnecting said plurality of elements in a loop-free configuration to form a multiple-input single-output array.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-10-11 | 1975-04-12 | 1975-10-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-10-11 | 1979-04-12 | 1979-10-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-10-11 | 1983-04-12 | 1983-10-12 | $7700.00 | Window Closed / Lapsed |