Redundancy circuit for semiconductor memory device

Claim 2

A redundancy circuit for generating a spare signal in a memory device having memory cells and spare memory cells, wherein some of the memory cells may be defective and wherein in response to the spare signal one or more space memory cells are addressed in the memory device, comprising: address lines for receiving addresses corresponding to the memory cells in the memory device, wherein one or more addresses correspond to defective memory cells; a reference line for generating the spare signal; a reference voltage circuit coupled to the reference line for supplying a first programming voltage and a spare signal voltage to the reference line; at least a pair of programmable transistors having an initially unprogrammed state and each having a gate, a source and a drain, the drains and sources of the transistors being coupled to the reference line and ground potential, respectively; high voltage driving circuits coupled to the gates of the transistors and to one or more address lines, wherein the transistors are programmed in response to the first programming voltage supplied by the reference voltage circuit and a second programming voltage supplied by the high voltage driving circuits, wherein the redundancy circuit produces the spare signal on the reference line in response to an address corresponding to a defective memory cell.

Claim 3

The redundancy circuit of claim 1, wherein the transistors comprise FLOTOX transistors.

Claim 4

The redundancy circuit of claim 1, wherein the transistors comprise EEPROM cells.

Claim 5

The redundancy circuit of claim 1, wherein: the reference voltage circuit comprises two inverters, wherein the reference voltage circuit outputs a first voltage level signal for generating the spare signal voltage and outputs a second voltage level signal for the first programming voltage for programming the transistors; and the high voltage driving circuit comprises four inverters and outputs a third voltage level signal for generating the spare signal voltage and outputs a fourth voltage level signal for the second programming voltage for programming the transistors.

Claim 6

The redundancy circuit of claim 4, wherein: the reference voltage circuit comprises: a first CMOS inverter coupled to a first voltage terminal, and a second CMOS inverter coupled to a second voltage terminal, and the high voltage driving circuit comprises: a third CMOS inverter coupled to the first voltage terminal, a fourth CMOS inverter coupled to a third voltage terminal, and fifth and sixth CMOS inverters coupled to the second voltage terminal.

Claim 7

The redundancy circuit of claim 5, wherein during programming of the transistors a first voltage level signal is supplied to the first voltage terminal, and a second voltage level signal having a voltage level higher than the voltage level of the first voltage level signal and capable of programming the transistors is supplied to the second and third voltage terminals, and wherein during addressing of the memory cells the first voltage level signal is supplied to each of the first, second and third voltage terminals.

Claim 8

The redundancy circuit of claim 5, wherein in response to-application of a first voltage level signal to the first voltage terminal, a second voltage level signal to the second voltage terminal, and the first voltage level signal to the third voltage terminal, the transistors are erased to an unprogrammed state.

Claim 9

A redundancy circuit for a memory device having memory cells and spare memory cells, wherein some of the memory cells may be defective, comprising: addressing means for supplying addressing signals for addressing the memory cells; a spare memory cell selecting line, wherein the spare memory cells are selected in response to a Spare memory selecting signal on the spare memory cell selecting line; a plurality of programmable and erasable elements coupled to the addressing means and coupled to the spare memory cell selecting line; a reference voltage circuit for supplying voltages to the selecting line, wherein the reference voltage circuit outputs the spare memory selecting signal of a first voltage level for selecting the spare memory cells and outputs a first programming signal of a second voltage level signal for programming the programmable and erasable elements; and programming means coupled to the programmable and erasable elements and the addressing means for programming the programmable and erasable elements with addresses of defective memory cells and for erasing the programmable and erasable elements, wherein the programming means provides a second programming signal of a third voltage level to the programmable and erasable elements for programming the programmable and erasable elements and provides an erasing signal of a fourth voltage level to the programmable and erasable elements for erasing the programmable and erasable elements; wherein, the programmable and erasable elements are programmed with the addresses of defective memory cells in response to the first and second programming signals and the address signals, and the programmable and erasable elements are erased in response to the erasing signal, and the spare memory cells are selected in response to the spare memory selecting signal and the address signals.

Claim 10

A redundancy circuit for a memory device having memory cells and spare memory cells, wherein some of the memory cells may be defective, comprising: addressing means for supplying addressing signals for addressing the memory cells; a spare memory cell selecting line, wherein the spare memory cells are selected in response to a Spare memory selecting signal on the spare memory cell selecting line; a plurality of programmable and erasable elements coupled to the addressing means and coupled to the spare memory cell selecting line; a reference voltage circuit for supplying voltages to the selecting line, wherein the reference voltage circuit outputs the spare memory selecting signal of a first voltage level for selecting the spare memory cells and outputs a first programming signal of a second voltage level signal for programming the programmable and erasable elements; and programming means coupled to the programmable and erasable elements and the addressing means for programming the programmable and erasable elements with addresses of defective memory cells and for erasing the programmable and erasable elements, wherein the programming means provides a second programming signal of a third voltage level to the programmable and erasable elements for programming the programmable and erasable elements and provides an erasing signal of a fourth voltage level to the programmable and erasable elements for erasing the programmable and erasable elements; wherein, the programmable and erasable elements are programmed with the addresses of defective memory cells in response to the first and second programming signals and the address signals, and the programmable and erasable elements are erased in response to the erasing signal, and the spare memory cells are selected in response to the spare memory selecting signal and the address signals.

Claim 11

The redundancy circuit of claim 8, wherein the programmable and erasable elements comprise EEPROM cells.

Claim 12

The redundancy circuit of claim 8, wherein the programmable and erasable elements comprise FLOTOX transistors.

Claim 13

The redundancy circuit of claim 8, wherein the reference voltage circuit comprises two inverter circuits, and the programming means comprises four inverter circuits.

Claim 14

The redundancy circuit of claim 11, wherein the reference voltage circuit comprises a first CMOS inverter circuit coupled to a first voltage terminal, and a second CMOS inverter circuit coupled to a second voltage terminal, and the programming means comprises a third CMOS inverter circuit coupled to the first voltage terminal, a fourth CMOS inverter circuit coupled to a third voltage terminal, and fifth and sixth CMOS inverter circuits coupled to the second voltage terminal.

Claim 15

The redundancy circuit of claim 12, wherein during programming of the programmable and erasable elements a first voltage level signal is supplied to the first voltage terminal, and a second voltage level signal having a voltage level higher than the voltage level of the first voltage level signal is supplied to the second and third voltage terminals, and wherein during addressing of the memory cells the first voltage level signal is supplied to each of the first, second, and third voltage terminals.

Claim 16

The redundancy circuit of claim 12, wherein the programmable and erasable elements are erased to an unprogrammed state in response to application of a first voltage level signal to the first voltage terminal, a second voltage level signal to the second voltage terminal, and the first voltage level signal to the third voltage terminal.

Claim 17

In a memory device having memory cells, some of which may be defective, one or more spare memory cells activated in response to a spare memory selection signal on a spare memory selection line, address lines for receiving addresses of the memory cells and the one or more spare memory cells, and programmable and erasable transistors coupled through a high voltage driving circuit to the address lines and the one or more spare memory cells, a method of selecting a spare memory cell, comprising the steps of: determining the address of a defective memory cell; applying a first programming signal to the spare memory selection line and applying a second programming signal to the programmable and erasable transistors by the high voltage driving circuit in accordance with the address of the defective memory cell, wherein the programmable and erasable transistors are programmed with the address of the defective memory cell; applying the spare memory selection signal to the spare memory selection line; applying to the address lines the address of the defective memory cell; and selecting the spare memory cell by maintaining the spare memory selection signal on the spare memory selection line.

Claim 18

In a memory device having memory cells, some of which may be defective, one or more spare memory cells activated in response to a spare memory selection signal on a spare memory selection line, address lines for receiving addresses of the memory cells and the one or more spare memory cells, and programmable and erasable transistors coupled through a high voltage driving circuit to the address lines and the one or more spare memory cells, a method of selecting a spare memory cell, comprising the steps of: determining the address of a defective memory cell; applying a first programming signal to the spare memory selection line and applying a second programming signal to the programmable and erasable transistors by the high voltage driving circuit in accordance with the address of the defective memory cell, wherein the programmable and erasable transistors are programmed with the address of the defective memory cell; applying the spare memory selection signal to the spare memory selection line; applying to the address lines the address of the defective memory cell; and selecting the spare memory cell by maintaining the spare memory selection signal on the spare memory selection line.

Claim 19

The method of claim 15, wherein the programmable and erasable transistors comprise EEPROM cells.

Claim 20

The method of claim 15, wherein the programmable and erasable transistors comprise FLOTOX transistors.