Transpose memory for DCT/IDCT circuit

Claim 2

A transpose memory for receiving elements of a matrix according to a first sequence order and for outputting elements to a first or second type of transform circuit according to a second sequence order comprising: four dual port memories, which memories each have a storage cell for storing an element of one fourth of said elements of said matrix, a first counter for writing each received matrix element, according to a first write counter order, in a particular storage cell of a first particular memory of said dual port memories which first particular memory corresponds to the matrix quadrant of said element, for said first type of transform circuit, and for writing each received matrix element, according to a second write counter order, in a particular storage cell of a second particular memory of said dual port memories which second particular memory corresponds to the matrix row and column evenness or oddness of said element, for said second type of transform circuit, and a second counter for simultaneously reading-out pairs of elements from particular storage cells of said memories according to said second sequence order.

Claim 3

The transpose memory of claim 1 wherein said first transform is a DCT and wherein said second transform is an IDCT.

Claim 4

The transpose memory of claim 1 wherein said second sequence order in which said matrix elements are outputted from said transpose memory is a transpose of said first sequence order in which said matrix elements are received at said transpose memory.

Claim 5

The transpose memory of claim 1 wherein said dual port memories are dual port RAMs.

Claim 6

The transpose memory of claim 1 wherein said transpose memory receives a sequence of matrices and wherein, for said first type of transform, said first counter writes said matrix elements of each odd received matrix in said storage cells according to said first write counter order and stores said matrix elements of each even received matrix in said storage cells according to a third write counter order which is a transpose of said first write counter order.

Claim 7

The transpose memory of claim 1 wherein said first and second counters are capable of counting simultaneously and wherein said counter orders of said first and second counters are synchronized with respect to each other and to the receipt of matrix elements at said transpose memory so that said second counter accesses said storage cells in a particular sequence so as to read-out elements of said received matrix only after said first counter accesses said particular storage cells for writing therein said matrix elements to be read-out by said second counter.

Claim 8

The transpose memory of claim 1 wherein said first counter outputs, in parallel, a count therein to write address input terminals of each of said four memories and wherein said first counter outputs appropriate enable signals to said memories for enabling the storage of a received matrix element in only one of said memories in a storage cell indicated by said count of said first counter.

Claim 9

The transpose memory of claim 1 wherein said first counter writes said received matrix elements in particular storage cells within each assigned dual port memory so that said second counter can read-out each of said matrix elements of each pair by outputting a single address to said-dual port memories.

Claim 10

The transpose memory of claim 1 wherein, according to said first ordering, said first counter writes matrix elements: from front rows and front columns of said received matrix into a first one of said dual port memories, from front rows and recent columns of said received matrix into a second one of said dual port memories, from recent rows and front columns of said received matrix into a third one of said dual port memories, and from recent rows and recent columns of said received matrix into a fourth one of said dual port memories.

Claim 11

The transpose memory of claim 9 wherein, according to said second ordering, said first counter writes matrix elements: from odd rows and odd columns of said received matrix into said first one of said memories, from odd rows and even columns of said received matrix into said second one of said memories, from even rows and odd columns of said received matrix into said third one of said memories, and from even rows and even columns of said received matrix into said fourth one of said memories.

Claim 12

The transpose memory of claim 1 wherein said second counter counts so as to read-out each pair two times.

Claim 13

The transpose memory of claim 11 wherein said second reading out of each pair is separated from said first reading out thereof by four counts of said second counter.

Claim 14

The transpose memory of claim 1 wherein said first counter writes said received matrix elements in said memories simultaneously while said second counter reads-out said pairs of elements from said memories.

Claim 15

A transpose memory for receiving elements of a matrix according to a first sequence order and for outputting elements to a first or second type of transform circuit according to a second sequence order comprising: four dual port memories, which memories each have a storage cell for storing element of one fourth of said elements of said matrix, a first counter for writing each received matrix element in a particular storage cell of a particular memory corresponding to the matrix quadrant of said element, for said first type of transform circuit, and for writing each received matrix element in a particular storage cell of a memory corresponding to the matrix row and column evenness or oddness of said element, for said second type of transform circuit, a second counter for simultaneously reading-out pairs of elements from particular storage cells of said memories according to said second sequence order, a first multiplexer receiving matrix elements read-out from a first one of said memories and a second one of said memories at first and second data inputs thereof and a first selector control signal from said second counter at a selection control input thereof, a second multiplexer receiving matrix elements read-out from a third one of said memories and matrix elements selected by said first multiplexer at first and second data inputs thereof and a second selector control signal from said second counter at a selector control input thereof, and a third multiplexer receiving matrix elements selected by said first multiplexer and matrix elements read-out from a fourth one of said memories at first and second data inputs thereof and said second selector control signal at a selector control input thereof, wherein said second counter outputs, in parallel, a count thereof to each of said memories and outputs particular first and second selector control signals for selecting a matrix element in a storage cell indicated by said count of said second counter in each of two particular ones of said memories.

Claim 16

A transpose memory for receiving elements of a matrix according to a first sequence order and for outputting elements to a first or second type of transform circuit according to a second sequence order comprising: four dual port memories, which memories each have a storage cell for storing element of one fourth of said elements of said matrix, a first counter for writing each received matrix element in a particular storage cell of a particular memory corresponding to the matrix quadrant of said element, for said first type of transform circuit, and for writing each received matrix element in a particular storage cell of a memory corresponding to the matrix row and column evenness or oddness of said element, for said second type of transform circuit, a second counter for simultaneously reading-out pairs of elements from particular storage cells of said memories according to said second sequence order, a first multiplexer receiving matrix elements read-out from a first one of said memories and a second one of said memories at first and second data inputs thereof and a first selector control signal from said second counter at a selection control input thereof, a second multiplexer receiving matrix elements read-out from a third one of said memories and matrix elements selected by said first multiplexer at first and second data inputs thereof and a second selector control signal from said second counter at a selector control input thereof, and a third multiplexer receiving matrix elements selected by said first multiplexer and matrix elements read-out from a fourth one of said memories at first and second data inputs thereof and said second selector control signal at a selector control input thereof, wherein said second counter outputs, in parallel, a count thereof to each of said memories and outputs particular first and second selector control signals for selecting a matrix element in a storage cell indicated by said count of said second counter in each of two particular ones of said memories.

Claim 17

A two dimensional transform circuit comprising: first and second one-dimensional transform circuits, said first one-dimensional transform circuit receiving an inputted matrix and outputting a first sequence of elements of a one-dimensionally transformed matrix according to a first sequence order, a transpose memory receiving said first sequence of matrix elements and comprising: four dual port memories, which memories each have a storage cell for storing an element of one fourth of said first sequence of elements of said matrix, a first counter for writing each received matrix element of said first sequence, according to a first write counter order, in a particular storage cell of a first particular memory of said dual port memories which first particular memory corresponds to the matrix quadrant of said element, if said second one-dimensional transform circuit is a first type of transform circuit, and for writing each received matrix element of said first sequence, according to a second write counter order, in a particular storage cell of a second particular memory of said dual port memories which second particular memory corresponds to the matrix row and column evenness or oddness of said element, if said second one-dimensional transform circuit is a second type of transform circuit, and a second counter for simultaneously reading-out a second sequence of pairs of elements of said one dimensionally transformed matrix from particular storage cells of said memories according to a second sequence order, and wherein said second one-dimensional transform circuit receives said second sequence of elements and outputs a two-dimensionally transformed matrix.

Claim 18

A two dimensional transform circuit comprising: first and second one-dimensional transform circuits, said first one-dimensional transform circuit receiving an inputted matrix and outputting a first sequence of elements of a one-dimensionally transformed matrix according to a first sequence order, a transpose memory receiving said first sequence of matrix elements and comprising: four dual port memories, which memories each have a storage cell for storing an element of one fourth of said first sequence of elements of said matrix, a first counter for writing each received matrix element of said first sequence, according to a first write counter order, in a particular storage cell of a first particular memory of said dual port memories which first particular memory corresponds to the matrix quadrant of said element, if said second one-dimensional transform circuit is a first type of transform circuit, and for writing each received matrix element of said first sequence, according to a second write counter order, in a particular storage cell of a second particular memory of said dual port memories which second particular memory corresponds to the matrix row and column evenness or oddness of said element, if said second one-dimensional transform circuit is a second type of transform circuit, and a second counter for simultaneously reading-out a second sequence of pairs of elements of said one dimensionally transformed matrix from particular storage cells of said memories according to a second sequence order, and wherein said second one-dimensional transform circuit receives said second sequence of elements and outputs a two-dimensionally transformed matrix.