US4903231A
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Transposition memory for a data processing circuit
Assignee: STMicroelectronics SA
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Filing: 1988-07-01
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Granted: 1990-02-20
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Expires: 2008-07-01
Abstract
Abstract A memory of nxn digital data, is adapted to receive the nxn data from a matrix block in line order after line and to output the data in column after column order. Such a memory is particularly useful for circuits carrying out digital transformations such as cosinus transformations wherein one must first carry out a line transformation then a column summation. The memory is constituted by a network of nxn registers REG(i,j) and of nxn multiplexers MUX(i,j); the registers are operated at a period T and the multiplexers at a period nxT. The connections between the memory inputs and outputs and the register network are alternatively connected at the period nxT in order that in a first phase the data are introduced and "horizontally" shifted inside the network and that in a second phase the data are introduced and "vertically" shifted.
Inventors
- 👤 Alain Artieri
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 05:31
CPC Classifications
G; G06; G06F; G06F12/00; G06F7/00; G06F7/76; G06F7/78; G06F17/00; G06F17/10; G06F17/16; G11; G11C; G11C19/00; G11C19/28
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
305 words
A transposition memory comprising n inputs (E0 to En-1) for receiving n×n data groups line after line, and n outputs (S0 to Sn-1) for outputting the data grouped according to successive columns, the data being the n×n data of a data square matrix, the data being further transmitted and processed in the form of electrical signals, further comprising a network of n×n registers (REG(i,j)) and of n×n multiplexers (MUX(i,j)), arranged in lines and columns, each register being associated with one multiplexer and being marked by its location in line i and its location in column j, the multiplexer (MUX(i,j)) having a first input connected with the output of register REG(i,j-1), a second input connected with the output of register REG(i+1,j) and an output connected with the input of register (REG(i,j)), the multiplexer output transmitting the status of the first input during a first operating phase (a) of the memory and further transmitting the status of the second input during a second phase (b), and the connections of the registers and multiplexers of the first and last lines and columns of the network being as follows: (a) the first inputs of the multiplexers of the first column (rank 0) are each connected with a respective input of the memory; (b) the outputs of the registers of the last column (rank n-1) are each connected through a respective switch with a respective output of the memory, this switch being closed during the first phase and open during the second phase; (c) the output of each register of the first line (rank 0) is connected, through a switch open during the first phase and closed during the second phase, with a respective output of the memory; (d) the second input of each multiplexer of the last line (rank n-1) is connected with a respective input of the memory.
Claim 2
Dependent Claim
305 words
A transposition memory comprising n inputs (E0 to En-1) for receiving n×n data groups line after line, and n outputs (S0 to Sn-1) for outputting the data grouped according to successive columns, the data being the n×n data of a data square matrix, the data being further transmitted and processed in the form of electrical signals, further comprising a network of n×n registers (REG(i,j)) and of n×n multiplexers (MUX(i,j)), arranged in lines and columns, each register being associated with one multiplexer and being marked by its location in line i and its location in column j, the multiplexer (MUX(i,j)) having a first input connected with the output of register REG(i,j-1), a second input connected with the output of register REG(i+1,j) and an output connected with the input of register (REG(i,j)), the multiplexer output transmitting the status of the first input during a first operating phase (a) of the memory and further transmitting the status of the second input during a second phase (b), and the connections of the registers and multiplexers of the first and last lines and columns of the network being as follows: (a) the first inputs of the multiplexers of the first column (rank 0) are each connected with a respective input of the memory; (b) the outputs of the registers of the last column (rank n-1) are each connected through a respective switch with a respective output of the memory, this switch being closed during the first phase and open during the second phase; (c) the output of each register of the first line (rank 0) is connected, through a switch open during the first phase and closed during the second phase, with a respective output of the memory; (d) the second input of each multiplexer of the last line (rank n-1) is connected with a respective input of the memory.
Claim 3
Dependent Claim
57 words
A memory according to claim 1, wherein each register is periodically filled with a new data and cleared of the previously recorded data within a time period T corresponding to the introduction frequency of the new data into the memory, and wherein the first and second operating phases of the memory each last a time period n×T.
Claim 4
Dependent Claim
100 words
A memory according to claim 2, wherein each register is constituted of m parallel sets of p elementary registers in cascade, each elementary register being capable of storing one data bit and being periodically operated in order to receive and transmit a new bit, the period being a period T/p wherein T is the introduction time period of new data into the memory, the input of register REG(i,j) being constituted by a bus of m conductors and its output being constituted by another bus of m conductors, the multiplexer inputs and outputs being also constituted by buses of m conductors.
Claim 5
Dependent Claim
91 words
A digital data processing circuit for carrying out, on one block of n×n data transmitted in the form of electrical signals, a data line summation followed with a data column summation of the result of the line summation, comprising a first operator (CTL) for the line summation, receiving the data to be processed, the outputs of the first operator being connected with the inputs of a memory, according to claim 1, and the outputs of the memory being connected with the inputs of a second operator (CTC) for the column summation.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-02-19 | 1993-08-21 | 1994-02-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-02-19 | 1997-08-21 | 1998-02-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-02-19 | 2001-08-21 | 2002-02-20 | $7700.00 | Window Closed / Lapsed |