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US5481447A Expired / Lapsed US ⏱️ 0.0 years remaining

Switched capacitance voltage multiplier with commutation

Assignee: Fluke Corp
•
Filing: 1995-04-27
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Granted: 1996-01-02
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Expires: 2015-04-27
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Abstract

Abstract A voltage multiplier is constructed using a series combination of capacitors and an associated switching circuit which provides for charging each capacitor in the series by sequentially connecting each capacitor to a d.c. input voltage. The d.c. input voltage of N volts is converted to an a.c. output voltage of peak-to-peak 2*(N+1) times the input voltage where N is the number of capacitors in the series. A pattern of sequential switching is chosen to generate a sequentially rising and falling voltage to form a half waveform. A commutator couples the half waveform to a pair of output terminals in an alternating polarity to form the completed a.c. output voltage.

Inventors

  • 👤 Hubertus A. Caris
  • 👤 Paulus J. M. Dost

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-02 20:27
CPC Classifications
H; H02; H02M; H02M3/00; H02M3/02; H02M3/04; H02M3/06; H02M3/07; H02M7/00; H02M7/42; H02M7/44; H02M7/48; H02M7/483; H02M7/4835

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 152 words
A d.c. to a.c. voltage multiplier circuit comprising: (a) a series network comprising a plurality of capacitors, each of said capacitors having a sufficient mount of capacitance to substantially maintain a charge voltage over a period of an a.c. output waveform; (b) a plurality of switches for selectably coupling said each of said capacitors to a d.c. input voltage for a selected charging time at least once during said period wherein said series network produces a sequentially increasing voltage followed by a sequentially decreasing voltage during one half of said period to form a waveform half; (c) a pair of output terminals; and (d) a commutator circuit interposed between said pair of output terminals and said series network, said commutator circuit selectively coupling said output terminals to receive said waveform half in a positive polarity followed by a negative polarity to form said a.c. output waveform at said pair of output terminals.
Claim 2
Dependent Claim 152 words
A d.c. to a.c. voltage multiplier circuit comprising: (a) a series network comprising a plurality of capacitors, each of said capacitors having a sufficient mount of capacitance to substantially maintain a charge voltage over a period of an a.c. output waveform; (b) a plurality of switches for selectably coupling said each of said capacitors to a d.c. input voltage for a selected charging time at least once during said period wherein said series network produces a sequentially increasing voltage followed by a sequentially decreasing voltage during one half of said period to form a waveform half; (c) a pair of output terminals; and (d) a commutator circuit interposed between said pair of output terminals and said series network, said commutator circuit selectively coupling said output terminals to receive said waveform half in a positive polarity followed by a negative polarity to form said a.c. output waveform at said pair of output terminals.
Claim 3
Dependent Claim 38 words
A d.c. to a.c. voltage multiplier circuit of claim 1 wherein said a.c. output waveform has a peak-peak voltage that is 2·(N+1) times said d.c. input voltage and N is the number of capacitors in said series network.
Claim 4
Dependent Claim 21 words
A d.c. to a.c. voltage multiplier circuit of claim 1 wherein the period of said a.c. output waveform is readily adjustable.
Claim 5
Dependent Claim 19 words
A d.c. to a.c. voltage multiplier circuit of claim 1 wherein said a.c. output waveform resembles a triangle wave.
Claim 6
Dependent Claim 19 words
A d.c. to a.c. voltage multiplier circuit of claim 1 wherein said a.c. output waveform resembles a sine wave.

References Cited (Backward Citations)

SU951602A1 Cited
GB2094076A Cited
US4504445A Cited
US4623824A Cited
US4994953A Cited
US5023768A Cited
US5095223A Cited
US5132895A Cited
US5414614A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1999-01-01 1999-07-03 2000-01-02 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2003-01-01 2003-07-03 2004-01-02 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2007-01-01 2007-07-03 2008-01-02 $7700.00 Window Closed / Lapsed

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