US5481243A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Braking system having variable intensity light and sound warning
Assignee: Individual
•
Filing: 1994-07-26
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Granted: 1996-01-02
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Expires: 2014-07-26
Abstract
Abstract A vehicle deceleration detection circuitry, upon which, a vehicle's rear brake lights will provide to a trailing vehicle, a continuous and variable intensity brake light as an indication of its braking pattern. In addition, in case of emergency braking, an additional light or strobe and an audible alert buzzer or horn will be turned on as to provide additional warning to a trailing vehicle. The vehicle deceleration detection circuit includes a microprocessor for providing continuous braking pattern indication, even if the vehicle is skidding on ice or oil; a condition which generates no G-force, which will not trip any mechanical detector.
Inventors
- 👤 Ranan R. Lurie
- 👤 Daniel Putnam
- 👤 Isac Tabib
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 17:58
CPC Classifications
B; B60; B60Q; B60Q1/00; B60Q1/26; B60Q1/44; B60Q1/444
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
332 words
A braking system for a vehicle for providing a combined audio and visual warning, comprising: a pulse generator means having a spinning wheel positioned in a U-shaped photoelectric sensor, for providing a pulsed square wave signal indicative of the speed of the vehicle; deceleration detection circuit means, having a vehicle velocity differential circuit comprising: a counter means, for counting the pulsed square wave signal in a given interval of time, for providing an n-bit counter signal; means for generating a load clock signal; a first buffer means, responsive to the n-bit counter signal, for storing a first buffer counter signal upon encountering said load clock signal; a second buffer means, for storing the first buffer counter signal from the first buffer means in the form of a second buffer counter signal upon encountering a subsequent load clock signal: said first buffer means storing a new first buffer counter signal responsive to the n-bit counter signal upon encountering said subsequent load clock signal; an add/subtract means, responsive to the new first buffer counter signal, and further responsive to the second buffer signal, for providing an add/subtract signal indicating the difference between the new first buffer counter signal and the second buffer counter signal indicative of differential vehicle velocity deceleration rate; programmable read only memory means, responsive to the add/subtract signal, and further responsive to a depression of a brake pedal, for providing a digital audio indication signal, and for further providing a digital visual indication signal; digital-to-analog converter means, responsive to the digital audio indication signal, for providing an analog audio indication signal, and further responsive to the digital visual indication signal, for providing an analog visual indication signal; visual brake warning means, responsive to the analog visual indication signal, for providing a variable visual warning display depending on the rate of deceleration of the vehicle; and audio brake warning means, responsive to the analog audio indication signal, for providing a variable audio warning depending on the rate of deceleration of the vehicle.
Claim 2
Dependent Claim
332 words
A braking system for a vehicle for providing a combined audio and visual warning, comprising: a pulse generator means having a spinning wheel positioned in a U-shaped photoelectric sensor, for providing a pulsed square wave signal indicative of the speed of the vehicle; deceleration detection circuit means, having a vehicle velocity differential circuit comprising: a counter means, for counting the pulsed square wave signal in a given interval of time, for providing an n-bit counter signal; means for generating a load clock signal; a first buffer means, responsive to the n-bit counter signal, for storing a first buffer counter signal upon encountering said load clock signal; a second buffer means, for storing the first buffer counter signal from the first buffer means in the form of a second buffer counter signal upon encountering a subsequent load clock signal: said first buffer means storing a new first buffer counter signal responsive to the n-bit counter signal upon encountering said subsequent load clock signal; an add/subtract means, responsive to the new first buffer counter signal, and further responsive to the second buffer signal, for providing an add/subtract signal indicating the difference between the new first buffer counter signal and the second buffer counter signal indicative of differential vehicle velocity deceleration rate; programmable read only memory means, responsive to the add/subtract signal, and further responsive to a depression of a brake pedal, for providing a digital audio indication signal, and for further providing a digital visual indication signal; digital-to-analog converter means, responsive to the digital audio indication signal, for providing an analog audio indication signal, and further responsive to the digital visual indication signal, for providing an analog visual indication signal; visual brake warning means, responsive to the analog visual indication signal, for providing a variable visual warning display depending on the rate of deceleration of the vehicle; and audio brake warning means, responsive to the analog audio indication signal, for providing a variable audio warning depending on the rate of deceleration of the vehicle.
Claim 3
Dependent Claim
35 words
A braking system according to claim 1, wherein the visual brake warning means includes tail lights having a series of concentrically arranged rings r1, r2, r3 which radially light depending on the rate of deceleration.
Claim 4
Dependent Claim
16 words
A braking system according to claim 1, wherein the audio brake warning means includes a horn.
References Cited (Backward Citations)
US2156751A
Cited
US2474610A
Cited
US3538496A
Cited
US3576528A
Cited
US3601794A
Cited
US3748643A
Cited
US3761875A
Cited
US4357594A
Cited
US4788526A
Cited
US4983953A
Cited
US5121100A
Cited
US5059947A
Cited
US5089805A
Cited
US5148147A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-01-01 | 1999-07-03 | 2000-01-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-01-01 | 2003-07-03 | 2004-01-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-01-01 | 2007-07-03 | 2008-01-02 | $7700.00 | Window Closed / Lapsed |