US5480826A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of manufacturing semiconductor device having a capacitor
Assignee: Renesas Electronics Corp
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Filing: 1995-02-03
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Granted: 1996-01-02
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Expires: 2015-02-03
Abstract
Abstract A semiconductor device includes a capacitor, of which insulator has an improved durability. In the semiconductor device, a capacitor lower electrode 11 of the cylindrical capacitor includes a standing wall portion 11b, which is formed of a polysilicon layer having a large crystal grain diameter (1000 Å-10000 Å).
Inventors
- 👤 Kazuyuki Sugahara
- 👤 Hideaki Arima
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 09:21
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/033; H10B12/30; H10B12/31; H10B12/318; H10D; H10D1/00; H10D1/01; H10D1/041; H10D1/042; H10D1/60; H10D1/62; H10D1/66; H10D1/68; H10D1/692; H10D1/711; H10D1/716; H10D62/00; H10D62/80; H10D62/83
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
166 words
A method of manufacturing a semiconductor device, comprising the steps of: forming a first insulating layer located on a major surface of a semiconductor substrate and having an opening which reaches said major surface of said semiconductor substrate; forming a first conductive layer located in said opening and being in contact with a surface of said first insulating layer; forming a second insulating layer above said first conductive layer; forming an amorphous silicon layer having a thickness of not more than 0.1 μm and covering at least said second insulating layer to form a lower electrode of a cylindrical capacitor; removing said amorphous silicon layer at least from an upper surface of said second insulating layer and thereby exposing said upper surface of said second insulating layer; removing said exposed second insulating layer by etching; forming a capacitor insulating layer covering said amorphous silicon layer; polycrystallizing said amorphous silicon layer to form a polysilicon layer; and forming a second conductive layer covering said capacitor insulating layer.
Claim 2
Independent Claim
166 words
A method of manufacturing a semiconductor device, comprising the steps of: forming a first insulating layer located on a major surface of a semiconductor substrate and having an opening which reaches said major surface of said semiconductor substrate; forming a first conductive layer located in said opening and being in contact with a surface of said first insulating layer; forming a second insulating layer above said first conductive layer; forming an amorphous silicon layer having a thickness of not more than 0.1 μm and covering at least said second insulating layer to form a lower electrode of a cylindrical capacitor; removing said amorphous silicon layer at least from an upper surface of said second insulating layer and thereby exposing said upper surface of said second insulating layer; removing said exposed second insulating layer by etching; forming a capacitor insulating layer covering said amorphous silicon layer; polycrystallizing said amorphous silicon layer to form a polysilicon layer; and forming a second conductive layer covering said capacitor insulating layer.
Claim 3
Dependent Claim
43 words
A manufacturing method of a semiconductor device according to claim 1, wherein said step of forming said amorphous silicon layer includes the step of forming an amorphous silicon layer having a surface roughness of about 10 Å or less, using a CVD method.
Claim 4
Dependent Claim
53 words
A manufacturing method of a semiconductor device according to claim 1, wherein said step of forming said polysilicon layer includes the step of forming a polysilicon layer having a crystal grain diameter in a range from about 1000 Å to about 10000 Å and a surface roughness of about 10 Å or less.
Claim 5
Independent Claim
194 words
A method of manufacturing a semiconductor device, comprising the steps of: forming a first insulating layer located on a major surface of a semiconductor substrate and having an opening which reaches said major surface of said semiconductor substrate; forming a first conductive layer located in said opening and being in contact with a surface of said first insulating layer; forming a second insulating layer above said first conductive layer; forming an etching mark on said second insulating layer; applying etching to said second insulating layer, using said etching mask as a mask, to remove said second insulating layer at a region, on which said etching mask is not formed, and to further remove said second insulating layer to form an undercut at a region, which is located under a side end of said second insulating layer and is adjacent said first insulating layer; forming a second conductive layer covering said second insulating layer after removal of said etching mask; removing said residual second insulating layer after patterning said second conductive layer; forming a capacitor insulating layer covering said first and second conductive layers; and forming a third conductive layer covering said capacitor insulating layer.
Claim 6
Independent Claim
194 words
A method of manufacturing a semiconductor device, comprising the steps of: forming a first insulating layer located on a major surface of a semiconductor substrate and having an opening which reaches said major surface of said semiconductor substrate; forming a first conductive layer located in said opening and being in contact with a surface of said first insulating layer; forming a second insulating layer above said first conductive layer; forming an etching mark on said second insulating layer; applying etching to said second insulating layer, using said etching mask as a mask, to remove said second insulating layer at a region, on which said etching mask is not formed, and to further remove said second insulating layer to form an undercut at a region, which is located under a side end of said second insulating layer and is adjacent said first insulating layer; forming a second conductive layer covering said second insulating layer after removal of said etching mask; removing said residual second insulating layer after patterning said second conductive layer; forming a capacitor insulating layer covering said first and second conductive layers; and forming a third conductive layer covering said capacitor insulating layer.
Claim 7
Dependent Claim
54 words
A method of manufacturing a semiconductor device according to claim 4, wherein said step of further removing said second insulating layer to a predetermined extent includes the step of etching said second insulating layer under a condition, in which a density of etching gas plasma is increased, for further removing said second insulating layer.
Claim 8
Dependent Claim
81 words
A method of manufacturing a semiconductor device according to claim 4, wherein said steps of forming said second conductive layer includes the steps of forming an amorphous silicon layer having a surface roughness of about 10 Å or less, using a CVD method; and polycrystallizing said amorphous silicon layer for ultimately forming said second conductive layer formed of a polysilicon layer having a crystal grain diameter of about 1000 Å-10000 Å and a surface roughness of about 10 Å or less.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-01-01 | 1999-07-03 | 2000-01-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-01-01 | 2003-07-03 | 2004-01-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-01-01 | 2007-07-03 | 2008-01-02 | $7700.00 | Window Closed / Lapsed |