Method of manufacture of high coupling ratio flash memory cell

Claim 1

A process of fabricating an array of floating gate flash memory devices on a substrate comprising: forming elongated spaced apart parallel ion implanted field implant regions in said substrate; forming elongated spaced apart parallel buried bitlines in said substrate orthogonally directed relative to said field implant regions; forming strips of silicon nitride from patterning a silicon nitride layer on the substrate and further patterning each strip into isolated squares; subjecting the substrate to thermal oxidation to form field oxide in all regions of the substrate surrounding the nitride squares so that said field oxide completely surrounds the nitride squares; removing the nitride squares to form hollow, square pockets and square channel regions in said substrate underlying said hollow pockets, where said channel regions have square dimensions of about 0.3 micrometers×0.3 micrometers; growing a silicon dioxide gate oxide layer on the exposed surfaces of said substrate in said pocket regions between field oxide regions, said silicon dioxide gate oxide layer having a thickness of from approximately one hundred twenty angstroms to three hundred angstroms; forming a plurality of first floating gate members from a first layer of polysilicon, the dimensions of said first floating gate members selected from square dimensions between about 0.6×0.6 micrometers and 0.7×0.7 micrometers, and rectangular dimensions of about 0.5 micrometers×0.7 micrometers, said first gate members being disposed over said gate oxide layer; forming a layer of interpolysilicon dielectric over said first floating gate members having a thickness of approximately one hundred fifty angstroms; forming an elongated layer of polysilicon over said layer of interpolysilicon dielectric and over said first gate members to form a second gate and a wordline, said second gate members extending perpendicular to said buried bitlines.