US5479044A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor circuit device capable of reducing influence of a parasitic capacitor
Assignee: Renesas Electronics Corp
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Filing: 1994-06-22
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Granted: 1995-12-26
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Expires: 2014-06-22
Abstract
Abstract A semiconductor circuit device includes a differential amplifier circuit having a first parasitic capacitor formed between the semiconductor substrate and a first resistor and a second parasitic capacitor formed between the semiconductor substrate and a second resistor. Each of the first and the second resistors is implemented by a wiring pattern over the substrate so that the first and the second parasitic capacitors are equivalent to each other.
Inventors
- 👤 Tetsuya Narahara
- 👤 Yasushi Matsubara
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 09:43
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/80; H10D84/811; H03; H03F; H03F3/00; H03F3/45; H03F3/45071; H03F3/45479; H10D88/00; H10W; H10W44/00; H10W44/401; H10W44/601
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
158 words
A semiconductor circuit device comprising a semiconductor substrate and a differential amplifier circuit which is formed on said semiconductor substrate and which comprises first and second input terminals and an output terminal, said differential amplifier circuit being supplied with an input signal through a first resistor connected to said first input terminal and producing an output signal through said output terminal, said differential amplifier circuit being supplied with said output signal through a second resistor connected between said second input terminal and said output terminal, said semiconductor circuit device having a first parasitic capacitor formed between said semiconductor substrate and said first resistor and a second parasitic capacitor formed between said semiconductor substrate and said second resistor, wherein: each of said first and said second resistors is implemented by a wiring pattern and is formed in a wiring layer formed over said semiconductor substrate so that said first and said second parasitic capacitors are equivalent to each other.
Claim 2
Dependent Claim
158 words
A semiconductor circuit device comprising a semiconductor substrate and a differential amplifier circuit which is formed on said semiconductor substrate and which comprises first and second input terminals and an output terminal, said differential amplifier circuit being supplied with an input signal through a first resistor connected to said first input terminal and producing an output signal through said output terminal, said differential amplifier circuit being supplied with said output signal through a second resistor connected between said second input terminal and said output terminal, said semiconductor circuit device having a first parasitic capacitor formed between said semiconductor substrate and said first resistor and a second parasitic capacitor formed between said semiconductor substrate and said second resistor, wherein: each of said first and said second resistors is implemented by a wiring pattern and is formed in a wiring layer formed over said semiconductor substrate so that said first and said second parasitic capacitors are equivalent to each other.
Claim 3
Dependent Claim
25 words
A semiconductor circuit device as claimed in claim 1, wherein said semiconductor substrate comprises a diffusion layer formed under said first and said second resistors.
Claim 4
Dependent Claim
41 words
A semiconductor circuit device as claimed in claim 2, another wiring pattern being formed over said wiring layer, wherein said semiconductor circuit device further comprises a conductive film formed between said another wiring pattern and said first and said second resistors.
Claim 5
Dependent Claim
39 words
A semiconductor circuit device as claimed in claim 3, wherein said diffusion layer and said conductive film are connected through a first contact hole, said conductive film and said another wiring pattern being connected through a second contact hole.
References Cited (Backward Citations)
FR1013381A
Cited
JPS59185432A
Cited
US4636738A
Cited
US4866502A
Cited
JPH02246409A
Cited
JPH0464997A
Cited
JPH05145351A
Cited
US5418385A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-12-25 | 1999-06-26 | 1999-12-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-12-25 | 2003-06-26 | 2003-12-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-12-25 | 2007-06-26 | 2007-12-26 | $7700.00 | Window Closed / Lapsed |