Patent US5477199A successfully refreshed from Google Patents.
US5477199A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Digital quadrature amplitude and vestigial sideband modulation decoding method and apparatus
Assignee: Cisco Technology Inc
•
Filing: 1994-10-07
•
Granted: 1995-12-19
•
Expires: 2014-10-07
Abstract
Abstract A synchronous detector for demodulating and decoding a digital data signal modulated either according to a vestigial sideband or a quadrature amplitude modulation scheme is based upon the principle of recognizing that a vestigial sideband signal may be regarded and treated as an offset-keyed QAM signal. The detector comprises a tuner for tuning to a center frequency symmetrically displaced within the transmitted digital data signal frequency spectrum and a decoder circuit selectively operating to reconstruct the transmitted digital data stream according to the duration of a transmitted data symbol. A related method of demodulating and decoding a modulated digital data stream comprises analogous steps of tuning to a center carrier frequency and selectively switching between in phase and quadrature arms of the demodulator such that the switch resides in one position or the other for a duration equal to half the duration of a transmitted data symbol. A related modulator for modulating a digital data signal either according to a vestigial sideband or quadrature amplitude modulation scheme comprises a switch for selectively switching an input digital data signal between real and imaginary arms and a modulator for modulating at center frequency. In one modulator embodiment, a noise cancellation circuit may be coupled between the real and imaginary arms.
Inventors
- 👤 Leo Montreuil
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 13:54
CPC Classifications
H; H03; H03C; H03C3/00; H03C3/38; H03C3/40; H03D; H03D1/00; H03D1/22; H03D1/2245; H03D1/2254; H04; H04L; H04L27/00; H04L27/0008; H04L27/02; H04L27/32; H04L27/34; H04L27/38; H04L27/3818; H04L27/3836; H04N; H04N21/00; H04N21/40; H04N21/41; H04N21/426; H03C3/02; H03C3/04; H03D2200/00; H03D2200/0001; H03D2200/0031; H03D3/00; H03D3/007; H03D3/02; H03D3/24; H03D3/241; H03D3/245
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
91 words
A synchronous detector for recovering a demodulated output digital data signal from a transmitted input digital data signal regardless of whether the transmitted input digital data stream is modulated according to a vestigial sideband or a quadrature amplitude modulation scheme, the synchronous detector comprising a tuner tuned to a center carrier frequency of a modulated data spectrum, the tuner comprising real and imaginary arms and a decoder for receiving digital data sequences from the real and imaginary arms, the decoder selectively operating according to the duration of a transmitted data symbol.
Claim 2
Dependent Claim
91 words
A synchronous detector for recovering a demodulated output digital data signal from a transmitted input digital data signal regardless of whether the transmitted input digital data stream is modulated according to a vestigial sideband or a quadrature amplitude modulation scheme, the synchronous detector comprising a tuner tuned to a center carrier frequency of a modulated data spectrum, the tuner comprising real and imaginary arms and a decoder for receiving digital data sequences from the real and imaginary arms, the decoder selectively operating according to the duration of a transmitted data symbol.
Claim 3
Dependent Claim
34 words
A synchronous detector according to claim 1 wherein the center carrier frequency of the modulated data spectrum comprises the frequency value of the center of symmetry of the transmitted information amplitude versus frequency spectrum.
Claim 4
Dependent Claim
39 words
A synchronous detector according to claim 1, the real and imaginary arms each comprising a mixer, an analog to digital converter coupled to the mixer and a data slicer for outputing in phase and quadrature digital data sequences respectively.
Claim 5
Dependent Claim
43 words
A synchronous detector according to claim 3, the real and imaginary arms each further comprising a Nyquist filter coupled to the outputs of the respective analog to digital converters for filtering the respective digital signals to be provided to the respective data slicers.
Claim 6
Dependent Claim
53 words
A synchronous detector according to claim 1, the decoder particularly comprising a two position switch for switching between an output of the real arm and an output of the imaginary arm, the switch remaining in each position for a duration 0.5T equal to one half the duration T of the transmitted data symbol.
Claim 7
Dependent Claim
44 words
A synchronous detector according to claim 5, the switch switching to the real arm position at time t equal to T, 2T, 3T and so on and switching to the imaginary arm position at time t equal to 0.5T, 1.5T, 2.5T and so on.
Claim 8
Dependent Claim
68 words
A modulator for modulating a digital data stream according to either a VSB or QAM modulation scheme, the modulator comprising a control circuit for alternately switching an input digital data stream to be modulated between a real arm and an imaginary arm and a modulator for modulating the digital data stream such that the carrier frequency is approximately symmetrically centered about the modulated data amplitude versus frequency spectrum.
Claim 9
Dependent Claim
68 words
A modulator for modulating a digital data stream according to either a VSB or QAM modulation scheme, the modulator comprising a control circuit for alternately switching an input digital data stream to be modulated between a real arm and an imaginary arm and a modulator for modulating the digital data stream such that the carrier frequency is approximately symmetrically centered about the modulated data amplitude versus frequency spectrum.
Claim 10
Dependent Claim
45 words
The modulator according to claim 7, the control circuit comprising a switch for switching between the real and imaginary arms such that the switch is connected to one or the other arm for a duration of one half the duration of a transmitted data symbol.
Claim 11
Dependent Claim
48 words
The modulator according to claim 8, the switch being connected to the real arm at time t equal to T, the duration of one symbol, 2T, 3T and so on and being connected to the imaginary arm at time t equal to 0.5T, 1.5T, 2.5T and so on.
Claim 12
Dependent Claim
19 words
The modulator according to claim 7, the real and imaginary arms each comprising a Nyquist filter and a mixer.
Claim 13
Dependent Claim
18 words
The modulator according to claim 7 further comprising a cancellation circuit coupled between the real and imaginary arms.
Claim 14
Dependent Claim
58 words
The modulator according to claim 11, the cancellation circuit comprising a jitter cancellation filter, a scaling circuit for scaling the output of the filter according to a factor k, which may comprise a resistor or an amplifier, and a summation circuit for summing the scaled output of the scaling circuit with the output of an imaginary arm filter.
Claim 15
Independent Claim
69 words
A method of demodulating and decoding a digital data stream modulated according to either a vestigial sideband or a quadrature amplitude modulation scheme, the method comprising the steps of tuning in each of an in phase and a quadrature arm of a demodulator to a center frequency of the modulated data spectrum and reconstructing the digital data stream according to the symbol rate of the transmitted digital data stream.
Claim 16
Independent Claim
69 words
A method of demodulating and decoding a digital data stream modulated according to either a vestigial sideband or a quadrature amplitude modulation scheme, the method comprising the steps of tuning in each of an in phase and a quadrature arm of a demodulator to a center frequency of the modulated data spectrum and reconstructing the digital data stream according to the symbol rate of the transmitted digital data stream.
Claim 17
Dependent Claim
48 words
A method of demodulating and decoding a digital data stream according to claim 13 wherein the digital data stream reconstruction step comprises the steps of converting the output of a mixer in each arm to a digital signal and deciding whether the recovered signal exceeds a predetermined threshold.
Claim 18
Dependent Claim
42 words
A method of demodulating and decoding a digital data stream according to claim 13 wherein the digital data stream reconstruction step comprises the step of switching between in phase and quadrature arms according to half the duration of a transmitted data symbol.
Claim 19
Dependent Claim
27 words
A method of demodulating and decoding a digital data stream according to claim 13 further comprising the step of subtracting transmitted carrier signal from a received signal.
Claim 20
Independent Claim
60 words
A method of modulating a digital data signal according to either a vestigial sideband or quadrature amplitude modulation scheme comprising the steps of switching to real and imaginary arms of a modulator according to the duration of a transmitted data symbol and modulating the digital data stream about a carrier frequency symmetrically centered in the modulated digital data signal spectrum.
Claim 21
Independent Claim
60 words
A method of modulating a digital data signal according to either a vestigial sideband or quadrature amplitude modulation scheme comprising the steps of switching to real and imaginary arms of a modulator according to the duration of a transmitted data symbol and modulating the digital data stream about a carrier frequency symmetrically centered in the modulated digital data signal spectrum.
Claim 22
Dependent Claim
26 words
A method of modulating a digital data signal according to claim 15 further comprising the step of canceling phase noise between the real and imaginary arms.
References Cited (Backward Citations)
US3902018A
Cited
US4253118A
Cited
US4323924A
Cited
US4339772A
Cited
US4405944A
Cited
US4490743A
Cited
US4602287A
Cited
US5040063A
Cited
US5043812A
Cited
US5136381A
Cited
US5144431A
Cited
US5087975A
Cited
US5181112A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-12-18 | 1999-06-19 | 1999-12-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-12-18 | 2003-06-19 | 2003-12-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-12-18 | 2007-06-19 | 2007-12-19 | $7700.00 | Window Closed / Lapsed |