Adiabatic dynamic noninverting circuitry

Claim 2

A non-inverter circuit, comprising: an input node receiving an input signal having one of two states; an output node producing an output signal having the same state as the input signal; a first clock node for receiving a first periodic clock signal adiabatically varying at predetermined rates of change between first and second levels; a second clock node for receiving a second periodic clock signal adiabatically varying at predetermined rates of change between third and fourth levels, the second clock signal having a predetermined phase shift with respect to the first clock signal; a first controllable switch of a first conductivity type in series with a second controllable switch of a second conductivity type, the first and second controllable switches connected in series between one of the clock nodes and the output node; the first controllable switch having a control terminal responsive to the other of the clock nodes and the second controllable switch having a control terminal responsive to the input node; and a rectification means connected between the output node and the one clock node.

Claim 3

An exclusive-or circuit, comprising: first and second input nodes receiving first and second input signals each having one of two states; an output node producing an output signal having a state which represents an exclusive-or function of the first and second input signals; a first clock node for receiving a first periodic clock signal adiabatically varying at predetermined rates of change between first and second levels; a second clock node for receiving a second periodic clock signal adiabatically varying at predetermined rates of change between third and fourth levels, the second clock signal having a predetermined phase shift with respect to the first clock signal; first and second controllable switches of a first conductivity type in series with a third controllable switch of a second conductivity type, the first, second, and third controllable switches connected in series between one of the clock nodes and the output node; the third controllable switch having a control terminal responsive to the other of the clock nodes and the first and second controllable switches each having respective control terminals responsive to a respective one of the first and second input nodes; and a rectification means connected between the output node and the one clock node.

Claim 4

An exclusive-or circuit, comprising: first and second input nodes receiving first and second input signals each having one of two states; an output node producing an output signal having a state which represents an exclusive-or function of the first and second input signals; a first clock node for receiving a first periodic clock signal adiabatically varying at predetermined rates of change between first and second levels; a second clock node for receiving a second periodic clock signal adiabatically varying at predetermined rates of change between third and fourth levels, the second clock signal having a predetermined phase shift with respect to the first clock signal; first and second controllable switches of a first conductivity type in series with a third controllable switch of a second conductivity type, the first, second, and third controllable switches connected in series between one of the clock nodes and the output node; the third controllable switch having a control terminal responsive to the other of the clock nodes and the first and second controllable switches each having respective control terminals responsive to a respective one of the first and second input nodes; and a rectification means connected between the output node and the one clock node.