Power source noise suppressing type semiconductor device

Claim 2

A power source noise suppressing semiconductor device comprising: a semiconductor chip having a surface, said semiconductor chip having a plurality of pads on the surface thereof, said pads including at least a first circuit pad and a second circuit pad, a first power source applied to said first circuit pad, a second power source applied to said second circuit pad, a voltage value of the second power source being independent of changes in a voltage value of the first power source; a plurality of leads, including at least one power source lead, each of said plurality of leads having an inner lead and an outer lead; and a plurality of electrically connecting means for electrically connecting one of said first circuit pad and said second circuit pad to an inner lead of one of said plurality of leads, said first circuit pad being connected to a first connection point of an inner lead of said power source lead by one of said electrically connecting means, said second circuit pad being connected to a second connection point of said inner lead of said power source lead by another of said electrically connecting means, said first and second connection points being spaced apart by a distance which allows a mutual inductance between said first and second connection points of said inner lead of said power source lead to become smaller than a self-inductance of an outer lead of said power source lead, wherein said distance is set to a value which is greater than a pitch value of said plurality of leads.

Claim 3

A device according to claim 3, wherein said distance is 0.5 mm or more.

Claim 4

A device according to claim 1, wherein said distance is set such that said mutual inductance becomes 1/10 of, or less than, said self-inductance, and wherein said inner lead of said power source lead traverses under said chip from one side of said chip to another side of said chip along the surface thereof.

Claim 5

A device according to claim 1, wherein said distance is set such that said mutual inductance becomes 1/10 of, or less than, said self-inductance, and wherein said inner lead of said power source lead traverses above said chip from one side of said chip to another side of said chip along the surface thereof.

Claim 6

A power source noise suppressing semiconductor device comprising: a semiconductor chip having a surface, said semiconductor chip having a plurality of pads on the surface thereof, said pads including at least a first circuit pad and a second circuit pad, a first power source applied to said first circuit pad, a second power source applied to said second circuit pad, a voltage value of the second power source being independent of changes in a voltage value of the first power source; a plurality of leads, including at least one power source lead, each of said plurality of leads having an inner lead and an outer lead; and a plurality of electrically connecting means for electrically connecting one of said first circuit pad and said second circuit pad to an inner lead of one of said plurality of leads, said first circuit pad being connected to a first connection point of an inner lead of said power source lead by one of said electrically connecting means, said second circuit pad being connected to a second connection point of said inner lead of said power source lead by another of said electrically connecting means, said first and second connection points being spaced apart by a distance which allows a mutual inductance between said first and second connection points of said inner lead of said power source lead to become smaller than a self-inductance of an outer lead of said power source lead, wherein said first and second circuit pads are both disposed on the surface of said chip along one side of said chip, and said inner lead of said power source lead is disposed along said one side, and wherein said outer lead of said power source lead is disposed in a first direction which is substantially perpendicular to a second direction along said one side, said inner lead is bent at an angle of 90 degrees relative to said outer lead, and said inner lead is disposed between said one side of said chip and said inner lead of another of said plurality of leads.

Claim 7

A power source noise suppressing semiconductor device comprising: a semiconductor chip having a surface, said semiconductor chip having a plurality of pads on the surface thereof, said pads including at least a first circuit pad and a second circuit pad, a first power source applied to said first circuit pad, a second power source applied to said second circuit pad, a voltage value of the second power source being independent of changes in a voltage value of the first power source; a plurality of leads, including at least one power source lead, each of said plurality of leads having an inner lead and an outer lead; and a plurality of electrically connecting means for electrically connecting one of said first circuit pad and said second circuit pad to an inner lead of one of said plurality of leads, said first circuit pad being connected to a first connection point of an inner lead of said power source lead by one of said electrically connecting means, said second circuit pad being connected to a second connection point of said inner lead of said power source lead by another of said electrically connecting means, said first and second connection points being spaced apart by a distance which allows a mutual inductance between said first and second connection points of said inner lead of said power source lead to become smaller than a self-inductance of an outer lead of said power source lead, wherein said first and second circuit pads are both disposed on the surface of said chip along one side of said chip, and said inner lead of said power source lead is disposed along said one side, and wherein said outer lead of said power source lead is disposed in a first direction which is substantially perpendicular to a second direction along said one side, said inner lead is bent at an angle of 90 degrees relative to said outer lead, and said inner lead is disposed between said one side of said chip and said inner lead of another of said plurality of leads.

Claim 8

A power source noise suppressing type semiconductor device comprising: a semiconductor chip having a surface, said semiconductor chip having a plurality of pads on the surface thereof, said pads including at least a first high voltage pad and a first low voltage pad, and a second high voltage pad and a second low voltage pad, a first power source applied to said first high voltage pad and said first low voltage pad, a second power source applied to said second high voltage pad and said second low voltage pad, a voltage value of said second power source being independent of changes in a voltage value of said first power source: a plurality of leads including at least a high voltage power source lead and a low voltage power source lead, each of said plurality of leads having an inner lead and an outer lead; and a plurality of electrically connecting means for electrically connecting one of said first high voltage pad, said first low voltage pad, said second high voltage pad and said second low voltage pad to an inner lead of one of said plurality of leads, said first and second high voltage and low voltage pads being connected respectively to first and second connection points of an inner lead of said high voltage power source lead by respective ones of said electrically connecting means, said high voltage first and second connection points being spaced apart by a distance which allows a mutual inductance between said high voltage first and second connection points of said inner lead of said high voltage power source lead to become smaller than a self-inductance of an outer lead of said high voltage power source lead, said low voltage first and second connection points being spaced apart by a distance which allows a mutual inductance between said low voltage first and second connection points of an inner lead of said low voltage power source lead to become smaller than a self-inductance of an outer lead of said low voltage power source lead, wherein said distance for each of said power source leads is set such that said mutual inductance becomes 1/10, or less than, said self-inductance, and wherein said semiconductor chip has four sides, said first high voltage pad and said second high voltage pad are respectively disposed on the surface of said chip at a first and a second predetermined location adjacent to two opposite sides of the four sides of said chip, and said first low voltage pad and said second low voltage pad are respectively disposed on the surface of said chip at a third and a fourth predetermined location adjacent to two opposite sides of the four sides of said chip.

Claim 9

A power source noise suppressing type semiconductor device comprising: a semiconductor chip having a surface, said semiconductor chip having a plurality of pads on the surface thereof, said pads including at least a first high voltage pad and a first low voltage pad, and a second high voltage pad and a second low voltage pad, a first power source applied to said first high voltage pad and said first low voltage pad, a second power source applied to said second high voltage pad and said second low voltage pad, a voltage value of said second power source being independent of changes in a voltage value of said first power source: a plurality of leads including at least a high voltage power source lead and a low voltage power source lead, each of said plurality of leads having an inner lead and an outer lead; and a plurality of electrically connecting means for electrically connecting one of said first high voltage pad, said first low voltage pad, said second high voltage pad and said second low voltage pad to an inner lead of one of said plurality of leads, said first and second high voltage and low voltage pads being connected respectively to first and second connection points of an inner lead of said high voltage power source lead by respective ones of said electrically connecting means, said high voltage first and second connection points being spaced apart by a distance which allows a mutual inductance between said high voltage first and second connection points of said inner lead of said high voltage power source lead to become smaller than a self-inductance of an outer lead of said high voltage power source lead, said low voltage first and second connection points being spaced apart by a distance which allows a mutual inductance between said low voltage first and second connection points of an inner lead of said low voltage power source lead to become smaller than a self-inductance of an outer lead of said low voltage power source lead, wherein said distance for each of said power source leads is set such that said mutual inductance becomes 1/10, or less than, said self-inductance, and wherein said semiconductor chip has four sides, said first high voltage pad and said second high voltage pad are respectively disposed on the surface of said chip at a first and a second predetermined location adjacent to two opposite sides of the four sides of said chip, and said first low voltage pad and said second low voltage pad are respectively disposed on the surface of said chip at a third and a fourth predetermined location adjacent to two opposite sides of the four sides of said chip.

Claim 10

A device according to claim 6, wherein said inner leads of said high voltage power source leads are bent at an angle of 90 degrees relative to said outer leads of said high voltage power source leads, and said inner leads of said low voltage power source leads are bent at an angle of 90 degrees relative to said outer leads of said low voltage power source leads.

Claim 11

A power source noise suppressing semiconductor device connected to a first and a second power source that respectively supply a first and a second voltage value to said semiconductor device, comprising: a semiconductor chip having a plurality of pads on a surface thereof, said pads including at least a first circuit pad and a second circuit pad, said first power source being applied to said first circuit pad, said second power source being applied to said second circuit pad, said second voltage value of said second power source being independent of changes in said first voltage value of said first power source; a plurality of leads, including at least one power source lead, each of said plurality of leads having an inner lead and an outer lead; and a plurality of connecting means for electrically connecting one of said first circuit pad and said second circuit pad to an inner lead of one of said plurality of leads, said first circuit pad being connected to a first connection point of an inner lead of said power source lead by one of said connecting means, said second circuit pad being connected to a second connection point of said inner lead of said power source lead by another of said connecting means, and said first and second connection points being spaced apart by a distance which allows a mutual inductance between said first and second connection points of said inner lead of said power source lead to become smaller than a self-inductance of an outer lead of said power source lead, wherein said distance is set to a value which is greater than a pitch value of said plurality of leads.

Claim 12

A power source noise suppressing semiconductor device connected to a first and a second power source that respectively supply a first and a second voltage value to said semiconductor device, comprising: a semiconductor chip having a plurality of pads on a surface thereof, said pads including at least a first circuit pad and a second circuit pad, said first power source being applied to said first circuit pad, said second power source being applied to said second circuit pad, said second voltage value of said second power source being independent of changes in said first voltage value of said first power source; a plurality of leads, including at least one power source lead, each of said plurality of leads having an inner lead and an outer lead; and a plurality of connecting means for electrically connecting one of said first circuit pad and said second circuit pad to an inner lead of one of said plurality of leads, said first circuit pad being connected to a first connection point of an inner lead of said power source lead by one of said connecting means, said second circuit pad being connected to a second connection point of said inner lead of said power source lead by another of said connecting means, and said first and second connection points being spaced apart by a distance which allows a mutual inductance between said first and second connection points of said inner lead of said power source lead to become smaller than a self-inductance of an outer lead of said power source lead, wherein said distance is set to a value which is greater than a pitch value of said plurality of leads.

Claim 13

A device according to claim 8, wherein said inner lead of said power source lead is positioned under said chip.

Claim 14

A device according to claim 8, wherein said inner lead of said power source lead is positioned above said chip.

Claim 15

A device according to claim 8, wherein said power source lead is connected to a low voltage side power source.

Claim 16

A device according to claim 8, wherein said power source lead is connected to a high voltage side power source.

Claim 17

A device according to claim 8, wherein said distance is set such that said mutual inductance is less than or equal to 1/10 of said self-inductance.

Claim 18

A device according to claim 13, wherein said inner lead of said power source lead traverses under said chip from one side of said chip to another side of said chip along the surface thereof.

Claim 19

A device according to claim 13, wherein said inner lead of said power source lead traverses above said chip from one side of said chip to another side of said chip along the surface thereof.

Claim 20

A device according to claim 8, wherein said distance is 0.5 mm or more.

Claim 21

A device according to claim 8, wherein a distance between said first connection point and said outer lead is shorter than a distance between said second connection point and said outer lead.

Claim 22

A device according to claim 8, wherein said first and second circuit pads are both disposed on the surface of said chip along one side of said chip, and said inner lead of said power source lead is disposed along said one side.

Claim 23

A device according to claim 8, wherein said first and second circuit pads are respectively disposed on the surface of said chip at a first and a second predetermined location on said chip.

Claim 24

A device according to claim 8, wherein said semiconductor chip has four sides, and wherein said first and second circuit pads are respectively disposed on the surface of said chip at a first and a second predetermined location adjacent to two different perpendicular sides of the four sides of said chip, and the inner lead of said power source lead is bent at an angle of 90 degrees relative to said outer lead of said power source lead.

Claim 25

A power source noise suppressing type semiconductor device connected to a first and a second power source that respectively supply a first and a second voltage value to said semiconductor device, comprising: a semiconductor chip, said semiconductor chip having a plurality of pads on a surface thereof, said pads including at least a first high voltage pad and a first low voltage pad, and a second high voltage pad and a second low voltage pad, said first power source being applied to said first and second high voltage pads, said second power source being applied to said first and second low voltage pad, said second voltage value of said second power source being independent of changes in said first voltage value of said first power source; a plurality of leads including at least a high voltage power source lead and a low voltage power source lead, each of said plurality of leads having an inner lead and an outer lead; and a plurality of connecting means for electrically connecting one of said pads to one of said inner leads of one of said leads, said first and second high voltage and low voltage pads being connected respectively to first and second connection points of said inner lead of said high voltage power source lead by respective ones of said connecting means, said high voltage first and second connection points being spaced apart by a distance which allows a mutual inductance between said high voltage first and second connection points of said inner lead of said high voltage power source lead to become smaller than a self-inductance of said outer lead of said high voltage power source lead, and said low voltage first and second connection points being spaced apart by a distance which allows a mutual inductance between said low voltage first and second connection points of said inner lead of said low voltage power source lead to become smaller than a self-inductance of said outer lead of said low voltage power source lead, said distance is set to a value which is greater than a pitch value of said leads.

Claim 26

A power source noise suppressing type semiconductor device connected to a first and a second power source that respectively supply a first and a second voltage value to said semiconductor device, comprising: a semiconductor chip, said semiconductor chip having a plurality of pads on a surface thereof, said pads including at least a first high voltage pad and a first low voltage pad, and a second high voltage pad and a second low voltage pad, said first power source being applied to said first and second high voltage pads, said second power source being applied to said first and second low voltage pad, said second voltage value of said second power source being independent of changes in said first voltage value of said first power source; a plurality of leads including at least a high voltage power source lead and a low voltage power source lead, each of said plurality of leads having an inner lead and an outer lead; and a plurality of connecting means for electrically connecting one of said pads to one of said inner leads of one of said leads, said first and second high voltage and low voltage pads being connected respectively to first and second connection points of said inner lead of said high voltage power source lead by respective ones of said connecting means, said high voltage first and second connection points being spaced apart by a distance which allows a mutual inductance between said high voltage first and second connection points of said inner lead of said high voltage power source lead to become smaller than a self-inductance of said outer lead of said high voltage power source lead, and said low voltage first and second connection points being spaced apart by a distance which allows a mutual inductance between said low voltage first and second connection points of said inner lead of said low voltage power source lead to become smaller than a self-inductance of said outer lead of said low voltage power source lead, said distance is set to a value which is greater than a pitch value of said leads.

Claim 27

A device according to claim 21, wherein said distance of each of said power source leads is set such that said mutual inductance is less than or equal to 1/10 of said self-inductance.

Claim 28

A device according to claim 22, wherein said semiconductor chip has four sides, and wherein said first high voltage pad and said second high voltage pad are respectively disposed on the surface of said chip at a first and a second predetermined location adjacent to two opposite sides of the four sides of said chip, and said first low voltage pad and said second low voltage pad are respectively disposed on the surface of said chip at a third and a fourth predetermined location adjacent to two opposite sides of the four sides of said chip.

Claim 29

A device according to claim 22, wherein said first high voltage and low voltage pads and said second high voltage and low voltage pads are respectively disposed on the surface of said chip along one side of said chip, and said inner leads of said high voltage and low voltage power source leads are disposed along said one side.

Claim 30

A device according to claim 22, wherein said first and second high voltage pads are respectively disposed on the surface of said chip near at a first and a second predetermined location adjacent to one side of said chip, said first and second low voltage pads are respectively disposed on the surface of said chip at a third and a fourth predetermined location adjacent to another side of said chip, and said high voltage and low voltage power source leads are disposed along said one side and said another side.

Claim 31

A device according to claim 22, wherein said semiconductor chip has four sides, and wherein said first and second high voltage pads are respectively disposed on the surface of said chip at a first and a second predetermined location adjacent to two sides thereof perpendicular to each other, an inner lead of said high voltage power source lead is bent at an angle of 90 degrees relative to an outer lead of said high voltage power source lead, said first and second low voltage pads are respectively disposed on the surface of said chip at a third and a fourth predetermined location adjacent to two sides thereof perpendicular to each other, and an inner lead of said low voltage power source lead is bent at an angle of 90 degrees relative to an outer lead of said low voltage power source lead.

Claim 32

A device according to claim 21, wherein said distance of each of said power source leads is set to a value which is greater than a pitch value of said leads.

Claim 33

A power source noise suppressing type semiconductor device connected to a first and a second power source that respectively supply a first and a second voltage value to said semiconductor device, comprising: a semiconductor chip, said semiconductor chip having a plurality of pads on a surface thereof, said pads including at least a first high voltage pad and a first low voltage pad, and a second high voltage pad and a second low voltage pad, said first power source being applied to said first and second high voltage pad, said second power source being applied to said first and second low voltage pad, said second voltage value of said second power source being independent of changes in said first voltage value of said first power source; a plurality of leads including at least a high voltage power source lead and a low voltage power source lead, each of said plurality of leads having an inner lead and an outer lead; and a plurality of connecting means for electrically connecting one of said pads to one of said inner leads of one of said leads, said first high voltage and low voltage pads being connected respectively to high voltage and low voltage first connection points of said inner leads of said high voltage and low voltage power source leads by respective ones of said connecting means, said second high voltage and low voltage pads being connected respectively to high voltage and low voltage second connection points of said inner leads of said low voltage and high voltage power source leads by respective ones of said connecting means, said high voltage first and second connection points being spaced apart by a distance which allows a mutual inductance between said high voltage first and second connection points of said inner lead of said high voltage power source lead to become smaller than a self-inductance of said outer lead of said high voltage power source lead, and said low voltage first and second connection points being spaced apart by a distance which allows the mutual inductance between said low voltage first and second connection points of said inner lead of said low voltage power source lead to become smaller than a self-inductance of said outer lead of said low voltage power source lead, said distance is set to a value which is greater than a pitch value of said plurality of leads.

Claim 34

A power source noise suppressing type semiconductor device connected to a first and a second power source that respectively supply a first and a second voltage value to said semiconductor device, comprising: a semiconductor chip, said semiconductor chip having a plurality of pads on a surface thereof, said pads including at least a first high voltage pad and a first low voltage pad, and a second high voltage pad and a second low voltage pad, said first power source being applied to said first and second high voltage pad, said second power source being applied to said first and second low voltage pad, said second voltage value of said second power source being independent of changes in said first voltage value of said first power source; a plurality of leads including at least a high voltage power source lead and a low voltage power source lead, each of said plurality of leads having an inner lead and an outer lead; and a plurality of connecting means for electrically connecting one of said pads to one of said inner leads of one of said leads, said first high voltage and low voltage pads being connected respectively to high voltage and low voltage first connection points of said inner leads of said high voltage and low voltage power source leads by respective ones of said connecting means, said second high voltage and low voltage pads being connected respectively to high voltage and low voltage second connection points of said inner leads of said low voltage and high voltage power source leads by respective ones of said connecting means, said high voltage first and second connection points being spaced apart by a distance which allows a mutual inductance between said high voltage first and second connection points of said inner lead of said high voltage power source lead to become smaller than a self-inductance of said outer lead of said high voltage power source lead, and said low voltage first and second connection points being spaced apart by a distance which allows the mutual inductance between said low voltage first and second connection points of said inner lead of said low voltage power source lead to become smaller than a self-inductance of said outer lead of said low voltage power source lead, said distance is set to a value which is greater than a pitch value of said plurality of leads.