Method and apparatus for inhibiting a predecoder when selecting a redundant row line

Claim 2

A circuit for replacing a defective signal path with a redundant signal path, comprising: a drive source; a predecoder coupled to said drive source and to a plurality of predecoder lines, said predecoder lines coupling said predecoder to a plurality of decoders, each of said decoders connected to a respective plurality of word lines, said predecoder and plurality of decoders decoding selected ones of a plurality of addressing signals and selecting at least one of a plurality of signal paths from said drive source to one of said respective plurality of word lines; and a redundant decoder connected to a redundant word line and coupled to said predecoder for responding to addressing signals corresponding to a defective signal path, said redundant decoder generating a decoding-inhibiting signal to said predecoder to block said predecoder from selecting at least one of said plurality of signal paths and said redundant decoder selecting a redundant signal path for coupling said drive source to said redundant word line.

Claim 3

The circuit of claim 1, wherein said predecoder is operable to receive each of a set of said addressing signals corresponding in number to said predecoder lines, a selected state of one of said set normally operable to enable the establishment of a signal from said drive source to at least one predecoder line, said decoding-inhibiting signal operable to block the establishment of the signal path by said selected state.

Claim 4

The circuit of claim 1, wherein said redundancy decoder comprises a plurality of addressing transistors, each of said addressing transistors operable by a respective addressing signal to couple a node to a supply of a first voltage, circuitry for establishing a second voltage at said node prior to coupling to said node to said supply; isolation devices for coupling respective ones of each said addressing transistors to said node, said redundant decoder programmable by selecting ones of said isolation devices to isolate respective transistors from said node such that addressing signals corresponding to said selected ones will be inoperable to couple said node to said supply of the first voltage; circuitry coupled to said node for generating said decoding-inhibiting signal based on the presence of said second voltage at said node; and circuitry coupled to said node for establishing a signal path including said redundant signal path based on the presence of said second voltage at said node.

Claim 5

The circuit of claim 3, wherein said supply of said first voltage is ground.

Claim 6

The circuit of claim 3, wherein said isolation devices each comprise a fuse for coupling a current path of a respective addressing transistor to said node, said redundant decoder programmable by blowing selected ones of said fuses.

Claim 7

The circuit of claim 1, wherein said redundant decoder is programmable for responding to either of two different sets of said addressing signals that each correspond to a defective signal path, said redundant decoder operable to select one of up to two redundant signal paths in response thereto.

Claim 8

An array of integrated circuits, comprising: an array area in which said integrated circuits are formed; a plurality of decoding circuits formed in said array area each for decoding selected ones of a plurality of addressing signals and each operable to select at least one of a plurality of signal paths to respective integrated circuits in response thereto, said decoding circuit including a predecoder coupled to a drive source and a plurality of decoders coupled to said predecoder by a plurality of predecoder lines, said predecoder disabled from establishing a signal path from said drive source to said decoders in response to said predecoder receiving a disable signal; for each decoding circuit, a redundant decoder formed in said array area and programmable for responding to predetermined ones of said addressing signals by generating said disable signal and by selecting a redundant signal path, at least one redundant integrated circuit coupled to said redundant signal path; and each said decoding circuit coupled to a respective redundant decoder for receiving said disable signal therefrom, said decoding circuit not decoding said predetermined ones of said addressing signals in response to receiving said disable signal, such that said drive source is routed to said redundant integrated circuit instead of an integrated circuit corresponding to said predetermined ones of said addressing signals.

Claim 9

An array of integrated circuits, comprising: an array area in which said integrated circuits are formed; a plurality of decoding circuits formed in said array area each for decoding selected ones of a plurality of addressing signals and each operable to select at least one of a plurality of signal paths to respective integrated circuits in response thereto, said decoding circuit including a predecoder coupled to a drive source and a plurality of decoders coupled to said predecoder by a plurality of predecoder lines, said predecoder disabled from establishing a signal path from said drive source to said decoders in response to said predecoder receiving a disable signal; for each decoding circuit, a redundant decoder formed in said array area and programmable for responding to predetermined ones of said addressing signals by generating said disable signal and by selecting a redundant signal path, at least one redundant integrated circuit coupled to said redundant signal path; and each said decoding circuit coupled to a respective redundant decoder for receiving said disable signal therefrom, said decoding circuit not decoding said predetermined ones of said addressing signals in response to receiving said disable signal, such that said drive source is routed to said redundant integrated circuit instead of an integrated circuit corresponding to said predetermined ones of said addressing signals.

Claim 10

A memory array, comprising: a drive source; a plurality of memory cell arrays arranged in rows and columns, each cell array having a plurality of row lines for accessing respective pluralities of memory cells; for each cell array, at least one decoding circuit for decoding selected ones of a plurality of addressing signals and selecting at least one of a plurality of signal paths from said drive source to at least one of said row lines in response thereto; for each decoding circuit, a predecoder coupled to said drive source and a plurality of decoders coupled to said predecoder by a plurality of predecoder lines, said predecoder disabled from establishing a signal path from said drive source to said decoders in response to said predecoder receiving a disable signal, a redundant decoder programmable for responding to addressing signals corresponding to a defective row line by both generating said disable signal and by coupling said drive source to a redundant row line; and said decoding circuit coupled to said redundant decoder for receiving said disable signal therefrom and disabled from decoding said addressing signals in response to receiving said disable signal.

Claim 11

A memory array, comprising: a drive source; a plurality of memory cell arrays arranged in rows and columns, each cell array having a plurality of row lines for accessing respective pluralities of memory cells; for each cell array, at least one decoding circuit for decoding selected ones of a plurality of addressing signals and selecting at least one of a plurality of signal paths from said drive source to at least one of said row lines in response thereto; for each decoding circuit, a predecoder coupled to said drive source and a plurality of decoders coupled to said predecoder by a plurality of predecoder lines, said predecoder disabled from establishing a signal path from said drive source to said decoders in response to said predecoder receiving a disable signal, a redundant decoder programmable for responding to addressing signals corresponding to a defective row line by both generating said disable signal and by coupling said drive source to a redundant row line; and said decoding circuit coupled to said redundant decoder for receiving said disable signal therefrom and disabled from decoding said addressing signals in response to receiving said disable signal.

Claim 12

The array of claim 8, wherein each said redundant decoder circuit is operable to enable the coupling of said drive source to one of up to two redundant row lines in the place of up to two defective row lines.

Claim 13

The array of claim 8, wherein said cell arrays, said decoding circuits and said redundant decoders are formed within an array area, said drive source formed exterior of said array area.

Claim 16

The method of claim 11, and further comprising the steps of: when no defective signal path exits, connecting a node to a supply of a first voltage by selected ones of a plurality of addressing transistors in response to said redundancy decoder receiving addressing signals corresponding to said selected ones of said addressing transistors; when a defective signal path is discovered, programming the redundant decoder by programming a plurality of isolation devices each associated with a respective addressing signal to isolate a respective addressing transistor from the node; receiving the addressing signals by the redundant decoder; blocking by the programmed isolation devices the connection of the supply of the first voltage to the node through addressing transistors corresponding to respective programmed isolation devices; and generating the disable signal and enabling a drive source to be connected to the redundant signal path both in response to the state of said node being other than the first voltage.

Claim 17

The method of claim 12, wherein the isolation devices each comprise a fuse, said step of programming the isolation devices comprising blowing selected ones of said fuses.

Claim 18

The method of claim 12, wherein said step of connecting the node to the supply of the first voltage comprises the step of pulling the node to ground.

Claim 19

The method of claim 12, and further comprising the step of enabling the connection of one of a plurality of redundant signal paths to a drive source in replacement of one of a plurality of respective defective signal paths.

Claim 22

The method of claim 16, and further comprising the steps of: organizing the memory cells into a plurality of arrays on a face of an integrated circuit chip to be disposed in rows and columns; for each cell array, disposing a decoding circuit and a redundant decoder in proximity thereto; forming a single drive source generator in a peripheral area of the chip outside of said plurality of arrays; and coupling the drive source generator to each of the redundant decoders and each of the decoding circuits in said plurality of arrays.