Data processing with a self-timed approach to spurious transitions

Claim 2

A digital electronic device, comprising: digital circuitry having a plurality of inputs and responsive to a logic transition at one of said inputs to produce at an output thereof a spurious logic transition ultimately followed, after a settling time has elapsed since said input logic transition, by a stable logic level; a transition detector for detecting an occurrence of a logic transition at any of said inputs and producing a detection signal indicative of said occurrence, said transition detector including a latch circuit having an output for producing said detection signal; a self-timed circuit connected to said latch circuit output for receiving said detection signal and, after delaying for an amount of time which is approximately equal to said settling time, producing a done signal; and switching circuitry having a data input connected to said output of said digital circuitry and having a control input for receiving said done signal from said self-timed circuit, said switching circuitry responsive to said done signal to connect said data input thereof to a data output thereof.

Claim 3

The device of claim 1, wherein said done signal produced by said self-timed circuit is a dual rail signal.

Claim 4

The device of claim 2, wherein said switching circuitry includes an n-channel pass-gate and a p-channel pass-gate arranged to provide parallel current paths between said data input and said data output of said switching circuitry, said n-channel pass gate and said p-channel pass-gate being controlled by said dual rail done signal so that said n-channel pass-gate and said p-channel pass-gate are both switched from their non-conductive states to their conductive states within a period of time no longer than a propagation delay of one of said pass gates.

Claim 5

The device of claim 1, including latching circuitry for applying said logic transitions to said inputs of said digital circuitry, said latching circuitry having a dock input connected to a clock signal, said clock signal also connected to a clock input of said latch circuit of said transition detector.

Claim 6

The device of claim 4, wherein said latch circuit of said transition detector includes a data input connected to a fixed logic level.

Claim 7

The device of claim 5, wherein said latch circuit of said transition detector includes a reset input connected to said done signal.

Claim 8

The device of claim 1, wherein said latch circuit includes a reset input connected to said done signal.

Claim 9

The device of claim 1, wherein said digital circuitry includes a parallel adder circuit.

Claim 10

The device of claim 8, wherein said parallel adder circuit is a CMOS circuit.

Claim 11

A data processing system, comprising: data processing circuitry for performing data processing operations; peripheral circuitry connected to said data processing circuitry for communication with said data processing circuitry; and said data processing circuitry including digital circuitry having a plurality of inputs and responsive to a logic transition at one of said inputs to produce at an output thereof a spurious logic transition ultimately followed, after a settling time has elapsed since said input logic transition, by a stable logic level, a transition detector for detecting an occurrence of a logic transition at any of said inputs and producing a detection signal indicative of said occurrence, said transition detector including a latch circuit having an output for producing said detection signal, a self-timed circuit connected to said latch circuit output for receiving said detection signal and, after delaying for an amount of time which is approximately equal to said settling time, producing a done signal, and switching circuitry having a data input connected to said output of said digital circuitry and having a control input for receiving said done signal from said self-timed circuit, said switching circuitry responsive to said done signal to connect said data input thereof to a data output thereof.

Claim 12

A data processing system, comprising: data processing circuitry for performing data processing operations; peripheral circuitry connected to said data processing circuitry for communication with said data processing circuitry; and said data processing circuitry including digital circuitry having a plurality of inputs and responsive to a logic transition at one of said inputs to produce at an output thereof a spurious logic transition ultimately followed, after a settling time has elapsed since said input logic transition, by a stable logic level, a transition detector for detecting an occurrence of a logic transition at any of said inputs and producing a detection signal indicative of said occurrence, said transition detector including a latch circuit having an output for producing said detection signal, a self-timed circuit connected to said latch circuit output for receiving said detection signal and, after delaying for an amount of time which is approximately equal to said settling time, producing a done signal, and switching circuitry having a data input connected to said output of said digital circuitry and having a control input for receiving said done signal from said self-timed circuit, said switching circuitry responsive to said done signal to connect said data input thereof to a data output thereof.

Claim 13

The system of claim 10, wherein said done signal produced by said self-timed circuit is a dual rail signal.

Claim 14

The system of claim 11, wherein said switching circuitry includes an n-channel pass-gate and a p-channel pass-gate arranged to provide parallel current paths between said data input and said data output of said switching circuitry, said n-channel pass gate and said p-channel pass-gate being controlled by said dual rail done signal so that said n-channel pass-gate and said p-channel pass-gate are both switched from their non-conductive states to their conductive states within a period of time no longer than a propagation delay of one of said pass gates.

Claim 15

The system of claim 10, wherein said data processing circuitry includes latching circuitry for applying said logic transitions to said inputs of said digital circuitry, said latching circuitry having a clock input connected to a clock signal, said clock signal also connected to a clock input of said latch circuit of said transition detector.

Claim 16

The system of claim 13, wherein said latch circuit of said transition detector includes a data input connected to a fixed logic level.

Claim 17

The system of claim 14, wherein said latch circuit of said transition detector includes a reset input connected to said done signal.

Claim 18

The system of claim 10, wherein said latch circuit includes a reset input connected to said done signal.

Claim 19

The system of claim 10, wherein said digital circuitry includes a parallel adder circuit.

Claim 20

They system of claim 17, wherein said parallel adder circuit is a CMOS circuit.