Data discriminating circuit and an optical receiver using the same

Claim 2

A data discriminating circuit for discriminating digital data signals comprising: a data input section for inputting a digital data signal; a clock distributor section for outputting first and second clock signals having different phases from each other; a first data discriminating/judging section for receiving the first clock signal from the clock distributor section and the input digital data signal from the data input section and providing a first discriminated digital data signal and a first result of discriminating the input digital data signal with the first clock signal; a second data discriminating/judging section for receiving the second clock signal from the clock distributor section and the input digital data signal from the data input section and providing a second discriminated digital data signal and a second result of discriminating the input digital data signal with the first clock signal; and a discriminated-data selecting section for receiving the first and second results of discriminating the input digital data signal respectively from the first and second data discriminating/judging sections and selectively outputting the first discriminated digital data signal or the second discriminated digital data signal based on the first and second results of discriminating the input digital data signal.

Claim 3

The data discriminating circuit according to claim 1, wherein each of the first and second data discriminating/judging sections includes: a data discriminating section for discriminating an input digital data signal from the data input section with a clock signal supplied from the clock distributor section; a data/clock phase-relation detecting and judging section for detecting and judging a phase relation between the input digital data signal and the clock signal, based on the data signal discriminated by the data discriminating section and the input digital data signal supplied from the data input section and for providing a detected and judged phase relation; and a phase-relation result processing section for producing a select control signal to control a selection of the first and second discriminated digital data signals in the discriminated-data selecting section from the detected and judged phase relation output from the data/clock phase-relation detecting and judging section and the input digital data signal.

Claim 4

The data discriminating circuit according to claim 2, wherein the data/clock phase-relation detecting and judging section has a data/clock phase-relation detecting section and first and second data/clock phase-relation judging sections, and the data/clock phase-relation detecting section produces a pulse having a pulse width corresponding to a phase difference between the digital data signal discriminated by the data discriminating section and the input gigital data signal, whereby based on a result of judgment of the phase relation between the input digital data signal and the clock signal from the pulse width in the first data/clock phase-relation judging section, a clock signal to be input to the second data/clock phase-relation judging section is controlled.

Claim 5

The data discriminating circuit according to claim 3, wherein the data discriminating section and the first and second data/clock phase-relation judging sections are each comprised a D-FF (flip-flop); the phase-relation result processing section includes an inverter for inverting input digital data signal, an EXOR gate to which outputs of the first and second data/clock phase-relation judging sections are input, and a D-FF having a D input terminal supplied with an output of the EXOR gate and a C input terminal supplied with an output of the inverter; and the discriminated-data selecting section has a multiplexer or a selector to which outputs of the first and second data discriminating/judging sections are input, and an RS-FF having an S input terminal supplied with the output of the first data discriminating/judging section, an R input terminal supplied with the output of the second data discriminating/judging section, whereby the multiplexer or selector is controlled by an output of the RS-FF to selectively output the output of the first data discriminating/judging section or the output of the second data discriminating/judging section.

Claim 6

The data discriminating circuit according to claim 3, wherein the clock distributor section at least has one input buffer supplied with a clock signal from a clock input section, and an inverter; and clock signals in mutually inverted states are respectively input to the data discriminating section and the first data/clock phase-relation judging section of each of the first and second data discriminating/judging sections.

Claim 7

The data discriminating circuit according to claim 3, wherein the clock distributor section at least has one input buffer supplied with a clock signal from a clock input section, a first clock buffer, delay means and a second clock buffer associated with a delayed clock signal output from the delay means; and clock signals respectively input to the data discriminating section and the first data/clock phase-relation judging section of each of the first and second data discriminating/judging sections have a phase difference corresponding to a delay time in the delay mans.

Claim 8

The data discriminating circuit according to claim 6, wherein the delay means comprises a semiconductor gate element, or a delay element having a fixed or variable delay amount.

Claim 9

The data discriminating circuit according to claim 3, wherein the clock distributor at least has one input buffer supplied with a clock signal from a clock input section, a first clock buffer, delay means, a second clock buffer associated with a delayed clock signal output from the delay means and an inverter; clock signals respectively input to the data discriminating section and the first data/clock phase-relation judging section of each of the first and second data discriminating/judging sections have a phase difference corresponding to a delay time in the delay means; and clock signals in mutually inverted states are respectively input to the data discriminating section and the first data/clock phase-relation judging section of each of the first and second data discriminating/judging sections.

Claim 10

The data discriminating circuit according to claim 3, wherein the data/clock phase-relation detecting section comprises an inverter and an EXOR gate having one input terminal supplied with input data from the data input section via the inverter and an other input terminal supplied with an inverted output of the discriminated data from the data discriminating section.

Claim 11

The data discriminating circuit according to claim 3, wherein the data/clock phase-relation detecting section comprises a NOR gate having one input terminal supplied with input data directly from the data input section and an other input terminal supplied with an inverted output of the discriminated data from the data discriminating section.

Claim 12

The data discriminating circuit according to claim 3, wherein the data/clock phase-relation detecting section comprises an inverter and an AND gate having one input terminal supplied with input data from the data input section via the inverter and an other input terminal supplied with a non-inverted output of the discriminated data from the data discriminating section.

Claim 13

The data discriminating circuit according to claim 3, wherein the data/clock phase-relation detecting section comprises an AND gate having one input terminal supplied with input data directly from the data input section and an other input terminal supplied with a non-inverted output of the discriminated data from the data discriminating section.

Claim 14

The data discriminating circuit according to claim 2, wherein the first and second clock signals have a phase difference of a half of a time slot with respect to at least a highest bit rate of the digital data signals to be discriminated.

Claim 15

The data discriminating circuit according to claim 13, wherein a clock signal of a first phase to be input to the data discriminating section in each of the first and second data discriminating/judging sections and a clock signal of a second phase to be input to a first D-FF in the data/clock phase-relation detecting and judging section each have a phase difference of a half a time slot with respect to at least a highest bit rate of the digital data signals to be discriminated, and two types of clock signals of a third phase to be input to a second D-FF in the data/clock phase-relation detecting and judging section each have a phase difference of a half a time slot with respect to at least the highest bit rate of the digital data signals to be discriminated; and each of the first and second data discriminating/judging sections has a clock phase controller for selectively outputting one of the two types of clock signals of the third phase in accordance with a discrimination result from the first D-FF.

Claim 16

The data discriminating circuit according to claim 14, wherein in each of the first and second data discriminating/judging sections, the clock signals to be respectively input to the first D-FF and the second D-FF are set to each have a phase difference of 1/4 of a time slot with respect to the highest bit rate of the digital data signals to be discriminated, and the clock phase controller performs control in such a way that the phase of the clock signal to be input to the second D-FF leads or lags by 1/4 of the time slot in accordance with the discrimination result from the first D-FF.

Claim 17

The data discriminating circuit according to claim 14, wherein the clock phase controllers of the first and second data discriminating/judging sections respectively include a common buffer supplied with a clock signal from a clock input section, first and second delay means supplied with an output of the buffer, and first and second EXOR gates having first input terminals respectively supplied with outputs of the first and second delay means and other input terminals respectively supplied with judgment results from the first data/clock phase-relation judging sections.

Claim 18

The data discriminating circuit according to claim 16, wherein the delay means comprises a semiconductor gate element, or a delay element having a fixed or variable delay amount.

Claim 19

The data discriminating circuit according to claim 14, wherein the clock phase controllers of the first and second data discriminating/judging sections respectively include a common buffer supplied with a clock signal from a clock input section, common delay means supplied with an output of the buffer, an inverter supplied with an output of the delay means, and first and second EXOR gates having first input terminals respectively supplied with an output of the inverter and the output of the delay means and other input terminals respectively supplied with judgment results from the first data/clock phase-relation judging sections.

Claim 20

The data discriminating circuit according to claim 14, wherein the clock phase controllers of the first and second data discriminating/judging sections respectively include a common buffer supplied with a clock signal from a clock input section, first and second delay means supplied with an output of the buffer, first and second clock buffers respectively supplied with outputs of the first and second delay means, and first and second multiplexers or selectors each supplied with outputs of the first and second clock buffers and respectively supplied with judgment results from the first data/clock phase-relation judging sections, whereby each of the first and second multiplexers or selectors selectively outputs one of the outputs of the first and second clock buffers in accordance with the associated judgment result.

Claim 21

The data discriminating circuit according to claim 14, wherein the data/clock phase-relation detecting section comprises an EXOR gate having one input terminal supplied with input data from the data input section and an other input terminal supplied with an inverted output of the discriminated data from the data discriminating section, and an inverted output of the clock phase controller is input to the first data/clock phase-relation judging section.

Claim 22

The data discriminating circuit according to claim 2, wherein the discriminated data selecting section has a synchronization protection circuit for receiving an output from the phase-relation result processing section.

Claim 23

The data discriminating circuit according to claim 21, wherein the synchronization protection circuit has a counter, and the discriminated-data selecting section selectively outputs the discriminated data from the first or second data discriminating/judging section when the counter counts the output of the phase-relation result processing section at least a predetermined number of times.

Claim 24

The data discriminating circuit according to claim 1, wherein the first and second clock signals have a phase difference of a half of a time slot with respect to at least a highest bit rate of the digital data signals to be discriminated.

Claim 25

An optical receiver comprising: an optical signal receiving section; an equalizer/amplifier for amplifying a photoelectrically converted electric signal from the optical signal receiving section to a predetermined level; a timing extractor for providing a timing clock signal; and a data discriminating circuit having a data input section for receiving an output of the equalizer/amplifier as an input digital data signal; a clock distributor section for receiving the timing clock signal output of the timing extractor and outputting first and second clock signals having different phases from each other; a first data discriminating/judging section for receiving the first clock signal from the clock distributor section and the input digital data signal from the data input section and providing a first discriminated digital data signal and a first result of discriminating the input digital data signal with the first clock signal; a second data discriminating/judging section for receiving the second clock signal from the clock distributor section and the input digital data signal from the data input section and providing a second discriminated digital data signal and a second result of discriminating the input digital data signal with the first clock signal; and a discriminated data selecting signal for receiving the first and second results of discriminating the input digital data signal respectively from the first and second data discriminating/judging sections and selectively outputting the first discriminated digital data signal or the second discriminated digital data signal based on the first and second results of discriminating the input digital data signal.

Claim 26

An optical receiver comprising: an optical signal receiving section; an equalizer/amplifier for amplifying a photoelectrically converted electric signal from the optical signal receiving section to a predetermined level; a timing extractor for providing a timing clock signal; and a data discriminating circuit having a data input section for receiving an output of the equalizer/amplifier as an input digital data signal; a clock distributor section for receiving the timing clock signal output of the timing extractor and outputting first and second clock signals having different phases from each other; a first data discriminating/judging section for receiving the first clock signal from the clock distributor section and the input digital data signal from the data input section and providing a first discriminated digital data signal and a first result of discriminating the input digital data signal with the first clock signal; a second data discriminating/judging section for receiving the second clock signal from the clock distributor section and the input digital data signal from the data input section and providing a second discriminated digital data signal and a second result of discriminating the input digital data signal with the first clock signal; and a discriminated data selecting signal for receiving the first and second results of discriminating the input digital data signal respectively from the first and second data discriminating/judging sections and selectively outputting the first discriminated digital data signal or the second discriminated digital data signal based on the first and second results of discriminating the input digital data signal.