Discrimination circuit for received data

Claim 1

A discrimination circuit for received data comprising: a multiple-instant discrimination unit including means for discriminating the amplitude of received data with respect to one or more specified discrimination levels, means for providing gate pulses defined by a pattern in the received data, means responsive to the amplitude discrimination result and the gate pulses for passing pulses of a high frequency clock signal for each of said discrimination levels, said high frequency clock signal having a frequency which is higher than that of a clock signal of said received data; a counter unit including means for counting pulses fed from said passing means said multiple-instant discrimination unit and for sending out values of respective bits of said received data to store the output from said counting means as values representing each data bit to be discriminated, with the capability of storing a specified number of bits by successively shifting said bits; a memory unit which receives the output from said counter unit and stores a bit to be discriminated as well as a specified number of succeeding bits while successively shifting them; a discrimination decision unit including means for determining the value of said bit to be discriminated according to the discrimination condition defined by the contents stored in said counter unit and a specified number of bits preceding said bit to be discriminated which have already been discriminated; an output unit including means for storing the output of said discrimination decision unit while successively shifting the stored bits, for sending out the leading bit in the stored bits as regenerated data for said received data, and for feeding back all of stored bits to said discrimination decision unit as already discriminated results of a specified number of bits preceding said bit to be discriminated.