Single chip controller-memory device and a memory architecture and methods suitable for implementing the same

Claim 2

A processing device disposed on a single chip comprising: a controller coupled to an address bus and a data bus; and a memory comprising: a plurality of independently addressable blocks of memory cells, each said block coupled to said address bus and having a selected number of output lines coupled to said data bus, said controller accessing a location comprising a selected number of said memory cells of each of a selected number of said blocks as required to support controller operation via said data bus with a single address word including both row and column address bits simultaneously presented on said address bus.

Claim 3

The device of claim 1 wherein said controller comprises a display controller.

Claim 4

The device of claim 1 wherein a selected said block comprises an array of random access memory cells.

Claim 5

The device of claim 1 wherein a selected said block comprises an array of read-only memory cells.

Claim 6

The device of claim 1 wherein a selected said block comprises an array of programmable read-only memory cells.

Claim 7

The device of claim 1 wherein each said block includes n number of output lines and said location comprises n number of said cells, wherein n is an integer greater than zero.

Claim 8

The device of claim 5 wherein said programmable read-only memory cells are erasable.

Claim 9

The device of claim 7 wherein said programmable read-only memory cells are electrically erasable.

Claim 10

The device of claim 1 wherein a selected said block comprises an array of flash memory cells.

Claim 11

A memory architecture comprising: a plurality of blocks of memory cells, each said block having a plurality of storage locations each for storing n-bit words of data and n number of data lines; and a plurality of address decoders, each said address decoder coupled to a corresponding one of said blocks, said address decoders allowing access by an associated processor through said data lines of a selected said location in a selected number of said blocks simultaneously in response to simultaneously received row and column address bits,

Claim 12

A memory architecture comprising: a plurality of blocks of memory cells, each said block having a plurality of storage locations each for storing n-bit words of data and n number of data lines; and a plurality of address decoders, each said address decoder coupled to a corresponding one of said blocks, said address decoders allowing access by an associated processor through said data lines of a selected said location in a selected number of said blocks simultaneously in response to simultaneously received row and column address bits,

Claim 13

The architecture of claim 10 wherein each of said address decoders accesses a selected said location in the corresponding said block in response to a different range of addresses.

Claim 14

The architecture of claim 10 wherein at least one of said blocks includes a plurality of repair cells.

Claim 15

The architecture of claim 10 and further comprising an address bus coupled to each of said address decoders.

Claim 16

The architecture of claim 10 and further comprising a data bus coupled to said output lines of each of said blocks.

Claim 17

The architecture of claim 14 wherein said plurality of blocks comprises x number of blocks and said data bus is m number of bits wide and wherein n equals m divided by x.

Claim 18

The architecture of claim 10 the number of said memory cells within each said block is equal.

Claim 19

The architecture of claim 10 wherein each said address comprises a plurality of row address bits, a plurality of column address bits and at least one block select bit, said row and column address bits simultaneously presented to said address decoders.

Claim 20

An integrated circuit comprising: a controller; an j-bit wide address bus coupled to an address port of said controller; an m-bit wide data bus coupled to a data port of said controller; and a memory comprising: z number blocks of memory cells, said cells of each said block organized as an array x number of rows and y number of columns, each said block having n number of data lines coupled to said data bus; and z number of address decoders coupled to said address bus, each of said decoders coupled to a corresponding said block, an address provided to said decoders allowing access to an n-bit storage location of a selected number of said blocks as required to support operation of said controller via said m-bit wide data bus.

Claim 21

An integrated circuit comprising: a controller; an j-bit wide address bus coupled to an address port of said controller; an m-bit wide data bus coupled to a data port of said controller; and a memory comprising: z number blocks of memory cells, said cells of each said block organized as an array x number of rows and y number of columns, each said block having n number of data lines coupled to said data bus; and z number of address decoders coupled to said address bus, each of said decoders coupled to a corresponding said block, an address provided to said decoders allowing access to an n-bit storage location of a selected number of said blocks as required to support operation of said controller via said m-bit wide data bus.

Claim 22

The integrated circuit of claim 18 and further comprising digital to analog converter circuitry coupled to an output of said controller.

Claim 23

The integrated circuit of claim 18 wherein said controller includes a color palette.

Claim 24

The integrated circuit of claim 18 wherein m equals z times n.

Claim 25

The integrated circuit of claim 18 wherein each said block of cells comprises an array of dynamic random access memory cells.

Claim 26

The integrated circuit of claim 18 wherein said controller comprises a display controller and said memory comprises a frame buffer.

Claim 27

The integrated circuit of claim 18 wherein said controller is constructed from random logic.

Claim 28

The integrated circuit of claim 18 wherein each of said blocks includes a plurality of redundant cells for replacing defective said cells within the corresponding said array.

Claim 29

The integrated circuit of claim 25 wherein said redundant cells are disposed in at least one column in a said block.

Claim 30

The integrated circuit of claim 18 wherein m equals n.

Claim 31

A processing system: a central processing unit; a system bus coupled to said processing unit; display generation apparatus; display control circuitry disposed on a single chip and coupled to said system bus and said display apparatus comprising: a display controller; an j-bit wide address bus coupled to an address pore of said controller; an m-bit wide data bus coupled to a data port of said controller; and a frame buffer memory comprising: z number blocks of memory cells, said cells of each said block organized as an array x number of rows and y number of columns, each said block having n number of data lines coupled to said data bus; and z number of address decoders coupled to said address bus, each of said decoders coupled to a corresponding said block, an address provided to said decoders allowing access to an n-bit storage location of a selected number of said blocks via said m-bit data bus, wherein said selected number of said blocks is determined as required to support operation of said controller.

Claim 32

A processing system: a central processing unit; a system bus coupled to said processing unit; display generation apparatus; display control circuitry disposed on a single chip and coupled to said system bus and said display apparatus comprising: a display controller; an j-bit wide address bus coupled to an address pore of said controller; an m-bit wide data bus coupled to a data port of said controller; and a frame buffer memory comprising: z number blocks of memory cells, said cells of each said block organized as an array x number of rows and y number of columns, each said block having n number of data lines coupled to said data bus; and z number of address decoders coupled to said address bus, each of said decoders coupled to a corresponding said block, an address provided to said decoders allowing access to an n-bit storage location of a selected number of said blocks via said m-bit data bus, wherein said selected number of said blocks is determined as required to support operation of said controller.

Claim 33

The system of claim 28 wherein said display generation apparatus comprises a digital to analog converter coupled to said display control circuitry and a CRT display device.

Claim 34

The system of claim 28 wherein said display generation apparatus comprises a digital to analog converter coupled to said display control circuitry and a liquid crystal display device.

Claim 35

The system of claim 28 wherein said blocks of memory cells comprise arrays of dynamic random access memory cells.

Claim 36

The system of claim 28 wherein said display control circuitry includes digital to analog conversion circuitry for driving said display generation apparatus.

Claim 37

The system of claim 28 wherein said display control circuitry includes a color palette.

Claim 40

The method of claim 34 and further comprising the step of repairing defective cells in at least one of said blocks prior to said step of retrieving.

Claim 41

The method of claim 35 wherein said step of repairing comprises a step of repairing by substitution.

Claim 42

The method of claim 34 wherein said step of retrieving comprises the step of retrieving a sequence of n-bit words by sequentially addressing said operational ones of said blocks.

Claim 43

The method of claim 34 wherein portions of each said n-bit words are retrieved from different ones of said n-bit locations.