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US5473513A Expired / Lapsed US ⏱️ 0.0 years remaining

Photosensitive array wherein chips are not thermally matched to the substrate

Assignee: Xerox Corp
•
Filing: 1994-12-19
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Granted: 1995-12-05
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Expires: 2014-12-19
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Abstract

Abstract Semiconductor chips, such as photosensor arrays in a full-width scanner, are mounted on a substrate to maintain reasonably consistent spacing among chips regardless of temperature conditions during use. After chips are tacked onto the substrate with uncured epoxy, the assembly is brought to a low temperature prior to the heating of the curing step. The technique permits design of the assembly to compensate for differences between the thermal coefficient of expansion of the chips and that of the substrate, while also minimizing mechanical stresses on the chips caused by heating in the course of use.

Inventors

  • 👤 Kraig A. Quinn

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-10 01:44
CPC Classifications
G; G06; G06K; G06K7/00; G06K7/10; G06K7/10544; G06K7/10821; G06K7/10841; H; H10; H10D; H10D62/00; H10D62/10; H10D62/117; H10W; H10W90/00; H10W72/00; H10W72/071; H10W72/073; H10W72/07331; H10W72/07337; H10W72/30; H10W72/351; H10W72/353; H10W72/354

Claims Analysis

Total Claims: 21
Claim 1
Independent Claim 50 words
An assembly comprising: a substrate; and a plurality of semiconductor chips attached to the substrate, each of the semiconductor chips being in contact with one another at a first temperature and being spaced from one another at an operating temperature, with the first temperature being lower than the operating temperature.
Claim 2
Dependent Claim 50 words
An assembly comprising: a substrate; and a plurality of semiconductor chips attached to the substrate, each of the semiconductor chips being in contact with one another at a first temperature and being spaced from one another at an operating temperature, with the first temperature being lower than the operating temperature.
Claim 3
Dependent Claim 23 words
An assembly as in claim 1, wherein the semiconductor chips comprise a material having a lower thermal coefficient of expansion than the substrate.
Claim 4
Dependent Claim 12 words
An assembly as in claim 1, wherein the substrate substantially comprises alumina.
Claim 5
Dependent Claim 19 words
An assembly as in claim 1, wherein each of the semiconductor chips defines a plurality of repetitive structures thereon.
Claim 6
Dependent Claim 35 words
An assembly as in claim 4, wherein, at the expected operating temperature of the semiconductor chips, the semiconductor chips define a gap therebetween less than the distance between individual repetitive structures on a semiconductor chip.
Claim 7
Dependent Claim 37 words
An assembly as in claim 4, wherein, at the expected operating temperature of the semiconductor chips, the semiconductor chips define a gap therebetween less than one-tenth of the distance between individual repetitive structures on a semiconductor chip.
Claim 8
Dependent Claim 12 words
An assembly as in claim 4, wherein the repetitive structures comprise photosites.
Claim 9
Dependent Claim 15 words
An assembly as in claim 4, wherein the repetitive structures comprise portions of ink-jet ejectors.
Claim 10
Dependent Claim 12 words
An assembly as in claim 4, wherein the repetitive structures comprise LEDs.
Claim 11
Dependent Claim 20 words
An assembly as in claim 1, a semiconductor chip defining a groove between a main surface and a surface thereof.
Claim 12
Dependent Claim 75 words
An assembly comprising: a substrate; and a plurality of semiconductor chips attached to the substrate and arranged in a linear array on the substrate, each of the semiconductor chips having a main surface attached to the substrate, and a side surface in contact with a neighboring chip in the linear array at a first temperature and spaced from the neighboring chip at an operating temperature, with the first temperature being lower than the operating temperature.
Claim 13
Dependent Claim 75 words
An assembly comprising: a substrate; and a plurality of semiconductor chips attached to the substrate and arranged in a linear array on the substrate, each of the semiconductor chips having a main surface attached to the substrate, and a side surface in contact with a neighboring chip in the linear array at a first temperature and spaced from the neighboring chip at an operating temperature, with the first temperature being lower than the operating temperature.
Claim 14
Dependent Claim 33 words
An assembly as in claim 11, wherein each of the semiconductor chips defines a plurality of repetitive structures evenly spaced thereon, the repetitive structures on each chip being oriented along the linear array.
Claim 15
Dependent Claim 34 words
An assembly as in claim 12, wherein, at the operating temperature, the side surfaces of neighboring semiconductor chips define a gap therebetween less than a distance between individual repetitive structures on a semiconductor chip.
Claim 16
Dependent Claim 36 words
An assembly as in claim 12, wherein, at the operating temperature, the side surfaces of neighboring semiconductor chips define a gap therebetween less than one-tenth of a distance between individual repetitive structures on a semiconductor chip.
Claim 17
Dependent Claim 12 words
An assembly as in claim 12, wherein the repetitive structures comprise photosites.
Claim 18
Dependent Claim 15 words
An assembly as in claim 12, wherein the repetitive structures comprise portions of ink-jet ejectors.
Claim 19
Dependent Claim 12 words
An assembly as in claim 12, wherein the repetitive structures comprise LEDs.
Claim 20
Dependent Claim 16 words
An assembly as in claim 11, wherein the first temperature is not less than -20° C.
Claim 21
Dependent Claim 21 words
An assembly as in claim 11, wherein the first temperature is not more than 80 celsius degrees below the operating temperature.

References Cited (Backward Citations)

US3769091A Cited
US4467342A Cited
US5063286A Cited
JPH02265275A Cited
US4990462A Cited
US4976802A Cited
US5057854A Cited
US5166865A Cited
US5192959A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1998-12-04 1999-06-05 1999-12-05 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2002-12-04 2003-06-05 2003-12-05 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2006-12-04 2007-06-05 2007-12-05 $7700.00 Window Closed / Lapsed

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