US5473277A
Expired / Lapsed
US
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Output circuit for providing a finally adjustable voltage
Assignee: Fujitsu Ltd
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Filing: 1994-04-05
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Granted: 1995-12-05
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Expires: 2014-04-05
Abstract
Abstract A constant voltage generator circuit comprises adjusting means for making fine adjustment of each back-gate voltage of transistors on the basis of external control signals, and a transistor circuit for outputting a constant voltage adjusted on the basis of the back-gate voltage. A constant voltage generator circuit comprises adjusting means for making fine adjustment of each back-gate voltage of transistors on the basis of external control signals; and a transistor circuit for outputting a constant voltage adjusted on the basis of the back-gate voltages, the transistor circuit including a plurality of N transistors with their respective gates and sources connected together, and a load element for dividing the power source voltage with a plurality of N transistors. Adjusting means comprises a plurality of N-1 switching circuits for supplying bias voltages individually to the back-gate of the first through (N-1)th transistors in the transistor circuit on the basis of the external control signal, and a switching element for stopping the operation of the Nth transistor in the transistor circuit on the basis of the external control signal. A semiconductor memory comprises memory means for storing information; and constant voltage generating means for supplying voltage to memory means, the constant voltage generating means including adjusting means for making fine adjustment of each back-gate voltage of a plurality of transistor on the basis of external control signals, and a transistor circuit for outputting the constant voltage adjusted on the basis of the back-gate voltages.
Inventors
- 👤 Kazuto Furumochi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 17:33
CPC Classifications
G; G11; G11C; G11C5/00; G11C5/14; G11C5/147; G05; G05F; G05F3/00; G05F3/02; G05F3/08; G05F3/10; G05F3/16; G05F3/20; G05F3/24; G05F3/242; H; H03; H03K; H03K2217/00; H03K2217/0018
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
176 words
An output voltage generator circuit, comprising: a transistor circuit for outputting an output voltage, said transistor circuit comprising a plurality of transistors connected in series, wherein a source of a first transistor of said plurality of transistors is connected to a drain of a second, transistor of said plurality of transistors, and wherein each of said transistors is connected in a diode configuration; and adjusting means connected to said transistor circuit, said adjusting means for separately adjusting a back-gate voltage of each transistor of said plurality of transistors, said adjusting means comprising switches connected to each of the plurality of transistors to selectively connect the backgate of said each transistor with a source of said each transistor or with a source of another transistor of said plurality of transistors which has a source voltage of at least one diode voltage threshold below the source of said each transistor, said back-gate voltages being controlled based upon control signals from an external source, wherein said transistor circuit outputs an output voltage based upon adjustments by said adjusting means.
Claim 2
Dependent Claim
176 words
An output voltage generator circuit, comprising: a transistor circuit for outputting an output voltage, said transistor circuit comprising a plurality of transistors connected in series, wherein a source of a first transistor of said plurality of transistors is connected to a drain of a second, transistor of said plurality of transistors, and wherein each of said transistors is connected in a diode configuration; and adjusting means connected to said transistor circuit, said adjusting means for separately adjusting a back-gate voltage of each transistor of said plurality of transistors, said adjusting means comprising switches connected to each of the plurality of transistors to selectively connect the backgate of said each transistor with a source of said each transistor or with a source of another transistor of said plurality of transistors which has a source voltage of at least one diode voltage threshold below the source of said each transistor, said back-gate voltages being controlled based upon control signals from an external source, wherein said transistor circuit outputs an output voltage based upon adjustments by said adjusting means.
Claim 3
Dependent Claim
26 words
An output voltage generator circuit as recited in claim 1, further comprising: a load element for dividing a power source voltage with said plurality of transistors.
Claim 4
Dependent Claim
21 words
An output voltage generator circuit as recited in claim 1, further comprising: a ROM fuse circuit for generating said control signals.
Claim 5
Dependent Claim
73 words
An output voltage generator circuit according to claim 2 or 3, wherein said adjusting means comprises: (a) a plurality of switching circuits respectively connected to said plurality of transistors for supplying bias voltages individually to back-gates of each of the plurality of transistors in said transistor circuit, based upon the control signals; and (b) a switching element for stopping an operation of a transistor in said transistor circuit based upon the control signals.
Claim 6
Dependent Claim
89 words
An output voltage generator circuit according to claim 2 or 3, wherein a first switching circuit of said adjusting means, based upon the control signals, biases a back-gate of the first transistor in said transistor circuit with one voltage selected from a group of voltages including a source voltage between the first and second serially-connected transistors, a source voltage between the second transistor and third transistor of said plurality of transistors, a source voltage between the two adjacent transistors of said plurality of transistors, and a power source voltage.
Claim 7
Dependent Claim
90 words
An output voltage generator circuit according to claim 2 or 3, wherein a second switching circuit of said adjusting means, based upon the control signals, biases a back-gate of the second transistor in said transistor circuit with one voltage selected from a group of voltages including of a source voltage between the second transistor and third transistor of said plurality of transistors, a source voltage between the third transistor and a fourth transistor, a source voltage between two adjacent transistors of said plurality of transistors, and a power source voltage.
Claim 8
Dependent Claim
61 words
An output voltage generator circuit according to claim 2 or 3, wherein a switching circuit of said adjusting means, based upon the control signals, biases a back-gate of one transistor of said transistor circuit with a voltage selected from a group of voltages including of a source voltage between the one transistor and an adjacent transistor; and a power source voltage.
Claim 9
Dependent Claim
25 words
An output voltage generator circuit according to claim 3, wherein said control signal is generated by programming the fuse elements of said ROM fuse circuit.
Claim 10
Dependent Claim
20 words
An output voltage generator circuit according to claim 2 or 3, wherein said transistor circuit comprising n-type field effect transistors.
Claim 11
Dependent Claim
199 words
A semiconductor memory comprising: (a) memory means for storing information; and (b) output voltage generating means for supplying voltage to said memory means, said output voltage generating means including a transistor circuit for outputting said output voltage, said transistor circuit comprising a plurality of transistors connected in series, wherein a source of a first transistor of said plurality of transistors is connected to a drain of a second transistor of said plurality of transistors, and wherein each of said transistors is connected in a diode configuration; and adjusting means connected to said transistor circuit, said adjusting meads for separately adjusting a back-gate voltage of each transistor of said plurality of transistors, said adjusting means comprising switches connected to each of the plurality of transistors to selectively connect the backgate of said each transistor with a source of said each transistor or with a source of another transistor of said plurality of transistors which has a source voltage of at least one diode voltage threshold below the source of said each transistor, said back-gate voltages being controlled based upon control signals from an external source, wherein said transistor circuit outputs an output voltage based upon adjustments by said adjusting means.
Claim 12
Dependent Claim
199 words
A semiconductor memory comprising: (a) memory means for storing information; and (b) output voltage generating means for supplying voltage to said memory means, said output voltage generating means including a transistor circuit for outputting said output voltage, said transistor circuit comprising a plurality of transistors connected in series, wherein a source of a first transistor of said plurality of transistors is connected to a drain of a second transistor of said plurality of transistors, and wherein each of said transistors is connected in a diode configuration; and adjusting means connected to said transistor circuit, said adjusting meads for separately adjusting a back-gate voltage of each transistor of said plurality of transistors, said adjusting means comprising switches connected to each of the plurality of transistors to selectively connect the backgate of said each transistor with a source of said each transistor or with a source of another transistor of said plurality of transistors which has a source voltage of at least one diode voltage threshold below the source of said each transistor, said back-gate voltages being controlled based upon control signals from an external source, wherein said transistor circuit outputs an output voltage based upon adjustments by said adjusting means.
Claim 13
Dependent Claim
27 words
A semiconductor memory according to claim 10, wherein said transistor circuit further comprises a load element for dividing a power source voltage with said plurality of transistors.
Claim 14
Dependent Claim
24 words
A semiconductor memory according to claim 10, wherein said output voltage generating means further comprises a ROM fuse circuit for generating said control signals.
References Cited (Backward Citations)
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| 3.5 Years (Year 4) | 1998-12-04 | 1999-06-05 | 1999-12-05 | $2000.00 | Window Closed / Lapsed |
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