Expanded microcomputer system for controlling radio frequency interference

Claim 2

A radio receiver for receiving an RF signal, comprising: receiving circuitry for receiving and demodulating the RF signal; a microcomputer coupled to the receiving circuitry for enabling and disabling the receiving circuitry at predetermined times; an expansion chip coupled to and controlled by the microcomputer for communicating therewith to further process the RF signal; and wherein communication between the microcomputer and the expansion chip occurs at a first speed when the receiving circuitry is enabled and at a second speed faster than the first speed when the receiving circuitry is disabled.

Claim 3

The radio receiver according to claim 1, further comprising a communication bus coupled between the microcomputer and the expansion chip for providing communications thereover at the first and second speeds.

Claim 4

The radio receiver according to claim 2, wherein the microcomputer comprises: a processing unit for generating a data signal having first and second voltage levels for transmission to the expansion chip and for generating a speed control signal having third and fourth voltage levels when the receiving circuitry is respectively disabled and enabled; and a bus interface coupled to the processing unit and the communication bus for processing the data signal to generate an output signal for transmission over the communication bus, wherein the output signal is characterized by first predetermined rise and fall times when the speed control signal is at the third voltage level and by second predetermined rise and fall times when the speed control signal is at the fourth voltage level, and wherein the second predetermined rise and fall times are faster than the first predetermined rise and fall times.

Claim 5

The radio receiver according to claim 3, wherein the bus interface comprises a dual speed bus driver circuit, comprising: a first terminal for receiving the data signal; a second terminal for receiving the speed control signal; a third terminal coupled to the communication bus for providing the output signal thereto; and driving means coupled between the first, second, and third terminals for driving the communication bus with a first current when the speed control signal is at the third voltage level and for driving the communication bus with a second current higher than the first current when the speed control signal is at the fourth voltage level.

Claim 6

The radio receiver according to claim 4, wherein the driving means comprises: a low speed transistor stage comprising: a first transistor for coupling a positive voltage to the third terminal when the data signal is at the first voltage level, thereby supplying the first current to the third terminal; and a second transistor for coupling the third terminal to ground when the data signal is at the second voltage level.

Claim 7

The radio receiver according to claim 5, wherein the driving means further comprises: a high speed transistor stage, comprising: a third transistor for coupling the positive voltage to the third terminal when the data signal is at the first voltage level and the speed control signal is at the fourth voltage level, thereby supplying the second current to the third terminal; and a fourth transistor for coupling the third terminal to ground when the data signal is at the second voltage level and the speed control signal is at the fourth voltage level.

Claim 8

The radio receiver according to claim 6, wherein: the second voltage level is greater than the first voltage level; and the fourth voltage level is greater than the third voltage level.

Claim 9

The radio receiver according to claim 6, wherein: the first and third transistors are n-channel field effect transistors; and the second and fourth transistors are p-channel field effect transistors.

Claim 10

The radio receiver according to claim 6, wherein the driving means further comprises: an inverter having an input coupled to the first terminal for inverting the data signal; a NAND gate having first and second inputs coupled to the second terminal and an output of the inverter and having an output coupled to a gate electrode of the third transistor; an AND gate having first and second inputs coupled to the first and second terminals and having an output coupled to a gate electrode of the fourth transistor; and wherein the first terminal is coupled to gate electrodes of the first and second transistors, source electrodes of the first and third transistors are coupled to the positive voltage, source electrodes of the second and fourth transistors are coupled to ground, and drain electrodes of the first, second, third, and fourth transistors are coupled to the third terminal.

Claim 11

The radio receiver according to claim 6, wherein: the processing unit further generates an enable signal having fifth and sixth voltage levels; the dual speed bus driver circuit further comprises a fourth terminal for receiving the enable signal; the driving means is disabled when the enable signal is at the fifth voltage level and the speed control signal is at the third voltage level; and the sixth voltage level is greater than the fifth voltage level and the fourth voltage level is greater than the third voltage level.

Claim 12

The radio receiver according to claim 10, wherein the driving means further comprises: first and second inverters having inputs coupled to the first terminal for inverting the data signal; a first NAND gate having first and second inputs coupled to the second terminal and an output of the first inverter and having an output coupled to a gate electrode of the first transistor; a second NAND gate having first and second inputs coupled to the fourth terminal and an output of the second inverter and having an output coupled to a gate electrode of the third transistor; a first AND gate having first and second inputs coupled to the first and second terminals and having an output coupled to a gate electrode of the second transistor; a second AND gate having first and second inputs coupled to the first and fourth terminals and having an output coupled to a gate electrode of the fourth transistor; and wherein source electrodes of the first and third transistors are coupled to the positive voltage, source electrodes of the second and fourth transistors are coupled to ground, and drain electrodes of the first, second, third, and fourth transistors are coupled to the third terminal.

Claim 13

A dual speed bus driver circuit for driving a communication bus, comprising: a first terminal for receiving a data signal having first and second voltage levels; a second terminal for receiving a speed control signal having third and fourth voltage levels; a third terminal coupled to the communication bus for providing an output signal thereto; and driving means coupled between the first, second, and third terminals for driving the communication bus with a first current when the speed control signal is at the third voltage level and for driving the communication bus with a second current higher than the first current when the speed control signal is at the fourth voltage level.

Claim 14

A dual speed bus driver circuit for driving a communication bus, comprising: a first terminal for receiving a data signal having first and second voltage levels; a second terminal for receiving a speed control signal having third and fourth voltage levels; a third terminal coupled to the communication bus for providing an output signal thereto; and driving means coupled between the first, second, and third terminals for driving the communication bus with a first current when the speed control signal is at the third voltage level and for driving the communication bus with a second current higher than the first current when the speed control signal is at the fourth voltage level.

Claim 15

The dual speed bus driver circuit according to claim 12, wherein the driving means comprises: a low speed transistor stage comprising: a first transistor for coupling a positive voltage to the third terminal when the data signal is at the first voltage level, thereby supplying the first current to the third terminal; and a second transistor for coupling the third terminal to ground when the data signal is at the second voltage level.

Claim 16

The dual speed bus driver circuit according to claim 13, wherein the driving means further comprises: a high speed transistor stage, comprising: a third transistor for coupling the positive voltage to the third terminal when the data signal is at the first voltage level and the speed control signal is at the fourth voltage level, thereby supplying the second current to the third terminal; and a fourth transistor for coupling the third terminal to ground when the data signal is at the second voltage level and the speed control signal is at the fourth voltage level.

Claim 17

The dual speed bus driver circuit according to claim 14, wherein: the second voltage level is greater than the first voltage level; and the fourth voltage level is greater than the third voltage level.

Claim 18

The dual speed bus driver circuit according to claim 14, wherein: the first and third transistors are n-channel field effect transistors; and the second and fourth transistors are p-channel field effect transistors.

Claim 19

The dual speed bus driver circuit according to claim 14, wherein the driving means further comprises: an inverter having an input coupled to the first terminal for inverting the data signal; a NAND gate having first and second inputs coupled to the second terminal and an output of the inverter and having an output coupled to a gate electrode of the third transistor; an AND gate having first and second inputs coupled to the first and second terminals and having an output coupled to a gate electrode of the fourth transistor; and wherein the first terminal is coupled to gate electrodes of the first and second transistors, source electrodes of the first and third transistors are coupled to the positive voltage, source electrodes of the second and fourth transistors are coupled to ground, and drain electrodes of the first, second, third, and fourth transistors are coupled to the third terminal.

Claim 20

The dual speed bus driver circuit according to claim 14, further comprising a fourth terminal for receiving a enable signal having fifth and sixth voltage levels, wherein the driving means is disabled when the enable signal is at the fifth voltage level and the speed control signal is at the third voltage level, and wherein the sixth voltage level is greater than the fifth voltage level and the fourth voltage level is greater than the third voltage level.

Claim 21

The dual speed bus driver circuit according to claim 18, wherein the driving means further comprises: first and second inverters having inputs coupled to the first terminal for inverting the data signal; a first NAND gate having first and second inputs coupled to the second terminal and an output of the first inverter and having an output coupled to a gate electrode of the first transistor; a second NAND gate having first and second inputs coupled to the fourth terminal and an output of the second inverter and having an output coupled to a gate electrode of the third transistor; a first AND gate having first and second inputs coupled to the first and second terminals and having an output coupled to a gate electrode of the second transistor; a second AND gate having first and second inputs coupled to the first and fourth terminals and having an output coupled to a gate electrode of the fourth transistor; and wherein source electrodes of the first and third transistors are coupled to the positive voltage, source electrodes of the second and fourth transistors are coupled to ground, and drain electrodes of the first, second, third, and fourth transistors are coupled to the third terminal.

Claim 24

The method according to claim 20, wherein step (b) comprises the steps of: (e) generating a first data signal at a first data rate for transmission over the communication bus; and (f) driving the communication bus with a first current such that the first data signal is characterized by first predetermined rise and fall times.

Claim 25

The method according to claim 21, wherein step (d) comprises the steps of: (g) generating a second data signal at a second data rate faster than the first data rate for transmission over the communication bus; and (h) driving the communication bus with a second current such that the second data signal is characterized by second predetermined rise and fall times, wherein the second current is higher than the first current and the second predetermined rise and fall times are faster than the first predetermined rise and fall times.