Patent US5471589A successfully refreshed from Google Patents.
US5471589A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Multiprocessor data processing system having nonsymmetrical channel(x) to channel(y) interconnections
Assignee: Unisys Corp
•
Filing: 1993-09-08
•
Granted: 1995-11-28
•
Expires: 2013-09-08
Abstract
Abstract A multiprocessor data processing system comprises a plurality of unsymmetrically connected data processing nodes; where the total number of nodes is more than 2n-1 and less than 2n, and n is an integer larger than two Each node has n input/output channels which respectively are channel(0), channel(1), channel(2), etc.; each node has a binary address bn-1. . . b1b0 which runs consecutively from node to node; each pair of nodes whose binary addresses differ by only one binary bit bx are interconnected by a channel(x) to channel(x) connection; and, at least one pair of nodes whose binary addresses differ by two binary bits bx and by are interconnected by a channel(x) to channel(y) connection, where x and y=0,1, . . . n-1. To establish a route from any one node to any other node, channels are selected which decrease the distance to the destination by two nodes or one node or maintain the same distance.
Inventors
- 👤 Isam W. Akkawi
- 👤 Scott H. Hayashida
- 👤 Vivek Ladha
- 👤 John E. Rudy
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 19:03
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/16; G06F15/163; G06F15/173; G06F15/17356; G06F15/17368; G06F15/17381
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
170 words
A multiprocessor data processing system comprising: a plurality of data processing nodes with the total number of nodes in said plurality being more than 2 n-1 and less than 2 n where n is an integer larger than two; each node having n input/output channels which respectively are channel(0), channel(1), . . . channel(n-1); and each node having a binary address b n-1 . . . b 1 b 0 which runs consecutively from node to node; all of said nodes being interconnected by said channels in an array which is unsymmetrical; each pair of nodes in said unsymmetrical array whose binary addresses differ by only one binary bit b x being interconnected by a channel(x) to channel(x) connection, where x=0,1, . . . n-1; and, at least one pair of nodes in said unsymmetrical array whose binary addresses differ by two binary bits b x and b y being interconnected by a channel(x) to channel(y) connection with no intervening node therebetween, where x and y=0,1, . . . n-1.
Claim 2
Dependent Claim
170 words
A multiprocessor data processing system comprising: a plurality of data processing nodes with the total number of nodes in said plurality being more than 2 n-1 and less than 2 n where n is an integer larger than two; each node having n input/output channels which respectively are channel(0), channel(1), . . . channel(n-1); and each node having a binary address b n-1 . . . b 1 b 0 which runs consecutively from node to node; all of said nodes being interconnected by said channels in an array which is unsymmetrical; each pair of nodes in said unsymmetrical array whose binary addresses differ by only one binary bit b x being interconnected by a channel(x) to channel(x) connection, where x=0,1, . . . n-1; and, at least one pair of nodes in said unsymmetrical array whose binary addresses differ by two binary bits b x and b y being interconnected by a channel(x) to channel(y) connection with no intervening node therebetween, where x and y=0,1, . . . n-1.
Claim 3
Dependent Claim
80 words
A data processing system according to claim 1 wherein each node includes: an input register which receives, from a first one of its channels, a header with a destination field and a distance field; and a control circuit which selects a second one of its channels for sending a modified header thereon, with said second channel being selected from the set of channels which shorten the distance to said destination by one or two or maintain the same distance thereto.
Claim 4
Dependent Claim
93 words
A data processing system according to claim 1 wherein each node includes: an input register which receives, from a first one of its channels, a header with a destination field and a distance field; and a transmitter which sends a modified header on a second one of its channels; and wherein to generate said modified header, each node further includes a conditional subtracter circuit which--a) subtracts two from said distance field if the selected channel forms a channel(x) to channel(y) connection to another node, and b) otherwise subtracts one from said distance field.
Claim 5
Dependent Claim
40 words
A data processing system according to claim 1 wherein the sum of said channel(x) to channel(x) connections plus said channel(x) to channel(y) connections from any particular node is within one of the sum of such connections from any other node.
Claim 6
Dependent Claim
22 words
A data processing system according to claim 1 wherein at least one node has multiple channel(x) to channel(y) connections to other nodes.
Claim 7
Dependent Claim
50 words
A data processing system according to claim 1 wherein every node, whose most significant address bit b n-1 is a one, has all of its channels connected to a channel of another node; and, only nodes whose most significant address bit b n-1 is a zero, have an unconnected channel.
Claim 8
Dependent Claim
36 words
A data processing system according to claim 1 wherein every node has its channel(0), channel(1), . . . channel(n-2) connected to a channel of another node; and, the only unconnected channel from any node is channel(n-1).
Claim 9
Dependent Claim
51 words
A data processing system according to claim 2 wherein to generate said modified header, each node further includes a conditional subtracter circuit which--a) subtracts two from said distance field if the selected channel forms a channel(x) to channel(y) connection to another node, and b) otherwise subtracts one from said distance field.
Claim 10
Dependent Claim
45 words
A data processing system according to claim 8 wherein said control circuit includes a) a mask register which identifies any of the nodes's channels that are unconnected, and b) a logic circuit coupled to said mask register which prevents the unconnected channels from being tried.
Claim 11
Dependent Claim
39 words
A data processing system according to claim 9 wherein the sum of said channel(x) to channel(x) connections plus channel(x) to channel(y) connections from any particular node is within one of the sum of such connections from any other node.
Claim 12
Dependent Claim
22 words
A data processing system according to claim 10 wherein at least one node has multiple channel(x) to channel(y) connections to other nodes.
Claim 13
Dependent Claim
50 words
A data processing system according to claim 11 wherein every node, whose most significant address bit b n-1 is a one, has all of its channels connected to a channel of another node; and, only nodes whose most significant address bit b n-1 is a zero, have an unconnected channel.
Claim 14
Dependent Claim
36 words
A data processing system according to claim 12 wherein every node has its channel(0), channel(1), . . . channel(n-2) connected to a channel of another node; and, the only unconnected channel from any node is channel(n-1).
References Cited (Backward Citations)
US4814980A
Cited
US4933933A
Cited
US5170482A
Cited
US5008882A
Cited
US5347450A
Cited
US5170393A
Cited
US5181017A
Cited
US5175733A
Cited
US5194867A
Cited
US5353283A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-11-27 | 1999-05-29 | 1999-11-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-11-27 | 2003-05-29 | 2003-11-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-11-27 | 2007-05-29 | 2007-11-28 | $7700.00 | Window Closed / Lapsed |