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US5471586A Expired / Lapsed US ⏱️ 0.0 years remaining

Interface system having plurality of channels and associated independent controllers for transferring data between shared buffer and peripheral devices independently

Assignee: Unisys Corp
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Filing: 1992-09-22
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Granted: 1995-11-28
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Expires: 2012-09-22
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Abstract

Abstract A device interface module provides multiple concurrently operating data transfer channels between multiple groups of peripheral devices and ad multiported buffer memory which communicates via an interface bus to other external modules of a computer system.

Inventors

  • 👤 Khorvash Sefidvash
  • 👤 Seyed H. Hashemi

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-02 15:59
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/10; G06F13/12; G06F13/124; G06F3/00; G06F3/06; G06F3/0601; G06F11/00; G06F11/07; G06F11/16; G06F11/20; G06F11/2002; G06F11/2007; G06F11/201; G06F11/2015; G06F3/0668; G06F3/0671; G06F3/0673

Claims Analysis

Total Claims: 7
Claim 1
Independent Claim 227 words
A device interface Module (DIM) for high speed data transfers between four groups of peripheral devices and first and second system busses, comprising: (a) four independent protocol-controller means connecting four groups of peripheral devices for data transfer operations, each said protocol-controller means including: (a1) FIFO register means for holding data destined to a buffer memory means and data destined for a connected peripheral device; (b) four channel bus means connecting, respectively, each of said protocol controller means to said buffer memory means wherein each said channel bus means includes: (b1) a dedicated script memory for holding commands from a control processor means to manage data transfer operations; wherein each of said protocol controller means executes the commands independently for controlling the data transfer operations between the peripheral devices connected thereto and the buffer memory means via said FIFO register means associated with each said protocol controller means; (c) bus controller logic means, coupling to each of said channel bus means, for granting equal time access period to each of said channel bus means; (d) said control processor means, coupling to each of said channel bus means, for generating said script commands for each of said protocol controller means to control said data transfer operations; and (e) said buffer memory means for temporarily storing data received from said first or second system busses destined for said peripheral devices.
Claim 2
Independent Claim 227 words
A device interface Module (DIM) for high speed data transfers between four groups of peripheral devices and first and second system busses, comprising: (a) four independent protocol-controller means connecting four groups of peripheral devices for data transfer operations, each said protocol-controller means including: (a1) FIFO register means for holding data destined to a buffer memory means and data destined for a connected peripheral device; (b) four channel bus means connecting, respectively, each of said protocol controller means to said buffer memory means wherein each said channel bus means includes: (b1) a dedicated script memory for holding commands from a control processor means to manage data transfer operations; wherein each of said protocol controller means executes the commands independently for controlling the data transfer operations between the peripheral devices connected thereto and the buffer memory means via said FIFO register means associated with each said protocol controller means; (c) bus controller logic means, coupling to each of said channel bus means, for granting equal time access period to each of said channel bus means; (d) said control processor means, coupling to each of said channel bus means, for generating said script commands for each of said protocol controller means to control said data transfer operations; and (e) said buffer memory means for temporarily storing data received from said first or second system busses destined for said peripheral devices.
Claim 3
Dependent Claim 35 words
The device interface module of claim 1 wherein said buffer memory means includes: (a) means for temporarily storing data received from said peripheral devices and destined for transfer to said first or second system busses.
Claim 4
Dependent Claim 52 words
The device interface module of claim 1 wherein each said script memory includes: (a) first and second address ports for communication respectively with said control processor means and said channel bus means; (b) first and second data ports means for communication respectively with said control processor means and said channel bus means.
Claim 5
Dependent Claim 242 words
A multiple device interface module system where a plurality of device interface modules communicate with first and second system busses, said system comprising: (a) a plurality of device interface modules wherein each device interface module includes: (a1) first and second I/O port means connected to said first and second system busses for receiving and/or sending data to/from an internal buffer memory means; (a2) said buffer memory means for storing data received from said first and second system busses and for storing data received from a plurality of groups of peripheral devices; (a3) four independent protocol-processor port means connecting four channel bus means to four groups of peripheral devices for data transfer operations; (a4) each of said four channel bus means for transferring data to/from said protocol-processor port means from/to said buffer memory means and including: (a4a) script memory means for holding commands and programs received from a control processor means to manage data transfer operations; wherein each of said protocol-processor port means executes the commands independently for controlling the data transfer operations between the peripheral devices connected thereto and the buffer memory means; (a5) bus control logic means, coupling to each of said channel bus means, for granting equal time access period to each of said channel bus means; and (a6) control processor means, coupling to each of said channel bus means, for generating said script commands and programs for each of said protocol controller means to control said data transfer operations.
Claim 6
Dependent Claim 242 words
A multiple device interface module system where a plurality of device interface modules communicate with first and second system busses, said system comprising: (a) a plurality of device interface modules wherein each device interface module includes: (a1) first and second I/O port means connected to said first and second system busses for receiving and/or sending data to/from an internal buffer memory means; (a2) said buffer memory means for storing data received from said first and second system busses and for storing data received from a plurality of groups of peripheral devices; (a3) four independent protocol-processor port means connecting four channel bus means to four groups of peripheral devices for data transfer operations; (a4) each of said four channel bus means for transferring data to/from said protocol-processor port means from/to said buffer memory means and including: (a4a) script memory means for holding commands and programs received from a control processor means to manage data transfer operations; wherein each of said protocol-processor port means executes the commands independently for controlling the data transfer operations between the peripheral devices connected thereto and the buffer memory means; (a5) bus control logic means, coupling to each of said channel bus means, for granting equal time access period to each of said channel bus means; and (a6) control processor means, coupling to each of said channel bus means, for generating said script commands and programs for each of said protocol controller means to control said data transfer operations.
Claim 7
Dependent Claim 70 words
The device interface module system of claim 4 wherein said plurality of device interface modules include: (a) means to connect a first protocol-controller port means of a first device interface module to one port of a selected peripheral device having two input/output ports; (b) means to connect a second protocol-controller port means of a second device interface module to a second port of said peripheral device having two input/output ports.

References Cited (Backward Citations)

US4484275A Cited
US4672535A Cited
US4672537A Cited
EP0427119A2 Cited
US5206943A Cited
WO1992004674A1 Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1998-11-27 1999-05-29 1999-11-28 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2002-11-27 2003-05-29 2003-11-28 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2006-11-27 2007-05-29 2007-11-28 $7700.00 Window Closed / Lapsed

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