Patent US5471245A successfully refreshed from Google Patents.
US5471245A
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Bulk charged modulated device (BCMD) image sensors with increased dynamic range
Assignee: Texas Instruments Inc
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Filing: 1994-05-19
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Granted: 1995-11-28
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Expires: 2014-05-19
Abstract
Abstract An image array with improved dynamic range has at least one photosite, at least one column sense line and at least one column clamp transistor. A source of the photosite is coupled to the column sense line. A source of the column clamp transistor is coupled to the photosite source. A drain of the column clamp transistor is coupled to a drain of the photosite. A gate of the column clamp transistor is provided for application of a φ cc signal. The φ cc signal is coupled through a capacitance to the column sense line.
Inventors
- 👤 Alan N. Cooper
- 👤 William P. McCracken
- 👤 Jaroslav Hynecek
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 22:46
CPC Classifications
H; H04; H04N; H04N25/00; H04N25/60; H04N25/62; H04N25/621; H04N25/70; H04N25/76
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
100 words
An image array having at least one photosite transistor, at least one column sense line and at least one column clamp transistor, wherein: a source of said photosite transistor is coupled to said column sense line; a source of said column clamp transistor is coupled to said photosite source; a drain of said column clamp transistor is coupled to a drain of said photosite transistor; a clocked voltage is applied to a gate of said column clamp transistor; and a variable current is coupled to said column sense line, the variable current is decreased when the clocked voltage is increased.
Claim 2
Dependent Claim
100 words
An image array having at least one photosite transistor, at least one column sense line and at least one column clamp transistor, wherein: a source of said photosite transistor is coupled to said column sense line; a source of said column clamp transistor is coupled to said photosite source; a drain of said column clamp transistor is coupled to a drain of said photosite transistor; a clocked voltage is applied to a gate of said column clamp transistor; and a variable current is coupled to said column sense line, the variable current is decreased when the clocked voltage is increased.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-11-27 | 1999-05-29 | 1999-11-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-11-27 | 2003-05-29 | 2003-11-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-11-27 | 2007-05-29 | 2007-11-28 | $7700.00 | Window Closed / Lapsed |