US5471094A
Expired / Lapsed
US
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Self-aligned via structure
Assignee: Renesas Electronics America Inc
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Filing: 1994-02-24
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Granted: 1995-11-28
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Expires: 2014-02-24
Abstract
Abstract A self-aligned via between interconnect layers in an integrated circuit allows a less precise masking alignment to be used to fabricate an integrated circuit with increased packing density and improved yield. In one embodiment, self-aligned vias are used to connect first and second interconnect layers in an SRAM memory cell.
Inventors
- 👤 Chuen-Der Lien
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 13:41
CPC Classifications
H; H10; H10B; H10B10/00; H10B10/15; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/063; H10W20/0633; H10W20/069; H10W20/0693; H10W20/40; H10W20/41; H10W20/42; Y; Y10; Y10S; Y10S257/00; Y10S257/903
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
182 words
A self-aligned via structure, comprising: a semiconductor substrate; a polysilicon first interconnect layer overlying one surface of said substrate, a portion of said first interconnect layer forming a gate of a metal oxide semiconductor field effect transistor; a first dielectric layer formed directly upon said first interconnect layer, said first dielectric layer having upper and lower surfaces and having an opening extending between said upper and lower surfaces, and said first dielectric layer having at least one edge aligned with one edge of said first interconnect layer; a polysilicon conductive plug formed within said opening, said conductive plug having an upper surface and having a lower surface contacting the upper surface of said first interconnect layer, and said conductive plug having at least one edge aligned with one edge of said first interconnect layer; and a second dielectric layer overlying said substrate surface, and overlying at least one edge of said first dielectric layer, at least one edge of said first interconnect layer, and at least one edge of said conductive plug, but not overlying the upper surface of said conductive plug.
Claim 2
Dependent Claim
182 words
A self-aligned via structure, comprising: a semiconductor substrate; a polysilicon first interconnect layer overlying one surface of said substrate, a portion of said first interconnect layer forming a gate of a metal oxide semiconductor field effect transistor; a first dielectric layer formed directly upon said first interconnect layer, said first dielectric layer having upper and lower surfaces and having an opening extending between said upper and lower surfaces, and said first dielectric layer having at least one edge aligned with one edge of said first interconnect layer; a polysilicon conductive plug formed within said opening, said conductive plug having an upper surface and having a lower surface contacting the upper surface of said first interconnect layer, and said conductive plug having at least one edge aligned with one edge of said first interconnect layer; and a second dielectric layer overlying said substrate surface, and overlying at least one edge of said first dielectric layer, at least one edge of said first interconnect layer, and at least one edge of said conductive plug, but not overlying the upper surface of said conductive plug.
Claim 3
Dependent Claim
16 words
The structure as in claim 1 wherein said first and second dielectric layers comprise silicon dioxide.
Claim 4
Dependent Claim
30 words
The structure as in claim 1, further comprising a second interconnect layer overlying said second dielectric layer, wherein said second interconnect layer contacts the upper surface of said conductive plug.
Claim 5
Dependent Claim
28 words
The structure as in claim 3 wherein the upper surface of said conductive plug is substantially the same level as the upper surface of said first dielectric layer.
Claim 6
Dependent Claim
16 words
The structure as in claim 4 wherein said first and second dielectric layers comprise silicon dioxide.
References Cited (Backward Citations)
US4914056A
Cited
US5189506A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-11-27 | 1999-05-29 | 1999-11-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-11-27 | 2003-05-29 | 2003-11-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-11-27 | 2007-05-29 | 2007-11-28 | $7700.00 | Window Closed / Lapsed |