Patent US5471085A successfully refreshed from Google Patents.
← Back to Patent Explorer
US5471085A Expired / Lapsed US ⏱️ 0.0 years remaining

Semiconductor device with polycrystalline silicon emitter conductive layer

Assignee: Mitsubishi Electric Corp
•
Filing: 1994-09-22
•
Granted: 1995-11-28
•
Expires: 2014-09-22
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract An n + buried layer is formed on a surface of p - semiconductor substrate. An n - epitaxial growth layer and an n + diffusion layer are formed on a surface of n + buried layer. A p - base region and p + external base region adjoining to each other are formed on a surface of n - epitaxial growth layer. An an n + emitter region is formed at a surface of p - base region. An emitter electrode is formed adjacently to n + emitter region. The emitter electrode is made of polycrystalline silicon doped with phosphorus at a concentration from 1×10 20 cm -3 to 6×10 20 cm -3 .

Inventors

  • 👤 Yoshiyuki Ishigaki
  • 👤 Hiroki Honda
  • 👤 Kimiharu Uga
  • 👤 Masahiro Ishida

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-07 21:24
CPC Classifications
H; H10; H10D; H10D48/00; H10D48/30; H10D48/32; H10D48/34; H10D10/00; H10D10/01; H10D10/051; H10D64/00; H10D64/20; H10D64/23; H10D64/231; H10D84/00; H10D84/01; H10D84/0107; H10D84/0109; H10D84/02; H10D84/03; H10D84/038

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 109 words
A semiconductor device comprising: a semiconductor substrate having a main surface; a collector impurity region of a first conductivity type formed at the main surface of said semiconductor substrate; a base impurity region of a second conductivity type formed at the main surface of said semiconductor substrate within said collector impurity region; an emitter impurity region of the first conductivity type formed at the main surface of said semiconductor substrate within said base impurity region; and a conductive layer adjoining to said emitter impurity region, said conductive layer having a polycrystalline silicon layer substantially uniformly doped with phosphorus at a concentration of at least 1×10 20 cm -3 .
Claim 2
Dependent Claim 109 words
A semiconductor device comprising: a semiconductor substrate having a main surface; a collector impurity region of a first conductivity type formed at the main surface of said semiconductor substrate; a base impurity region of a second conductivity type formed at the main surface of said semiconductor substrate within said collector impurity region; an emitter impurity region of the first conductivity type formed at the main surface of said semiconductor substrate within said base impurity region; and a conductive layer adjoining to said emitter impurity region, said conductive layer having a polycrystalline silicon layer substantially uniformly doped with phosphorus at a concentration of at least 1×10 20 cm -3 .
Claim 3
Dependent Claim 42 words
The semiconductor device according to claim 1, wherein said conductive layer is formed of a polycrystalline silicon layer doped with phosphorus, and said phosphorus is contained in said polycrystalline silicon layer at a concentration of at most 6×10 20 cm -3 .
Claim 4
Dependent Claim 50 words
The semiconductor device according to claim 1, wherein said conducive layer has a polycrystalline silicon layer doped with phosphorus and a silicide layer formed on said polycrystalline silicon layer, and said phosphorus is contained in said polycrystalline silicon layer at a concentration of at most 1×10 21 cm -3 .
Claim 5
Dependent Claim 95 words
The semiconductor device according to claim 1, further comprising: a first insulating layer formed on the main surface of said semiconductor substrate; a second insulating layer formed on said first insulating layer and having a different etch characteristic from said first insulating layer; and a third insulating layer formed on said second insulating layer having a different etch characteristic from said second insulating layer; wherein said first, second and third insulating layers have an aperture reaching said emitter impurity region, and said conductive layer is in contact with said emitter impurity region through said aperture.
Claim 6
Dependent Claim 30 words
The semiconductor device according to claim 4, wherein said first and third insulating layers each include a silicon oxide film, and said second insulating layer includes a silicon nitride film.

References Cited (Backward Citations)

US4299024A Cited
US4927776A Cited
US5258644A Cited
JPH02105464A Cited
US5150184A Cited
JPH021160A Cited
JPH03201528A Cited
JPH04152531A Cited
JPH04278576A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1998-11-27 1999-05-29 1999-11-28 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2002-11-27 2003-05-29 2003-11-28 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2006-11-27 2007-05-29 2007-11-28 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag