US5469075A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Testable embedded microprocessor and method of testing same
Assignee: LSI Corp
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Filing: 1994-11-29
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Granted: 1995-11-21
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Expires: 2014-11-29
Abstract
Abstract A technique of gaining direct access to the inputs and outputs of an embedded microprocessor, otherwise buried behind additional logic, is disclosed. Multiplexers are provided for at least the embedded microprocessor inputs and outputs. In a test mode, the multiplexers connect device input and output pads directly to the embedded microprocessor inputs and outputs. In a normal operating mode, the multiplexers connect the additional logic to the input and output pads. Preferably, in order to standardize design criteria, multiplexers are provided on all of the inputs and outputs of the microprocessor which may become embedded behind additional logic. Additionally, it is possible in the test mode to control the additional logic to a well defined state. The invention provides a simple way to isolate the embedded microprocessor from the rest of the logic and test it thoroughly using test vectors that have already been developed for the stand-alone microprocessor.
Inventors
- 👤 Timothy P. Oke
- 👤 II Russell E. Cummings
- 👤 Nachum M. Gavrielov
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 16:00
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/22; G06F11/2205; G06F11/2236
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
247 words
An integrated circuit comprising: a die having an input pad and an output pad; a microprocessor disposed on said die and having an input and an output; additional logic disposed on said die and having a first output, a second output, a first input that is connected to said input pad and a second input that is connected to said output of said microprocessor; an input multiplexer for selectively connecting said input pad or said first output of said additional logic to said input of said microprocessor; an output multiplexer for selectively connecting said output of said microprocessor or said second output of said additional logic to the output pad; and means for forcing said additional logic to a predefined state; in which said input multiplexer and said output multiplexer have control inputs that are responsive to a control signal having a normal state or a test state; when said control signal has said normal state, said input multiplexer is controlled to connect said first output of said additional logic to said input of said microprocessor, and said output multiplexer is controlled to connect said second output of said additional logic to said output pad; when said control signal has said test state, said input multiplexer is controlled to connect said input pad to said input of said microprocessor, and said output multiplexer is controlled to connect said output of said microprocessor to said output pad and said means forces said additional logic to said predefined state.
Claim 2
Dependent Claim
247 words
An integrated circuit comprising: a die having an input pad and an output pad; a microprocessor disposed on said die and having an input and an output; additional logic disposed on said die and having a first output, a second output, a first input that is connected to said input pad and a second input that is connected to said output of said microprocessor; an input multiplexer for selectively connecting said input pad or said first output of said additional logic to said input of said microprocessor; an output multiplexer for selectively connecting said output of said microprocessor or said second output of said additional logic to the output pad; and means for forcing said additional logic to a predefined state; in which said input multiplexer and said output multiplexer have control inputs that are responsive to a control signal having a normal state or a test state; when said control signal has said normal state, said input multiplexer is controlled to connect said first output of said additional logic to said input of said microprocessor, and said output multiplexer is controlled to connect said second output of said additional logic to said output pad; when said control signal has said test state, said input multiplexer is controlled to connect said input pad to said input of said microprocessor, and said output multiplexer is controlled to connect said output of said microprocessor to said output pad and said means forces said additional logic to said predefined state.
Claim 3
Dependent Claim
255 words
An integrated circuit comprising: a die having an input pad and an output pad; a macrofunctional unit that is formed on the die and has an input and an output; additional logic that is formed on the die and has a first output, a second output, a first input that is connected to the input pad and a second input that is connected to said output of the macrofunctional unit; an input switch for selectively connecting the input pad or said first output of the additional logic to said input of the macrofunctional unit; an output switch for selectively connecting said output of the macrofunctional unit or said second output of the additional logic to the output pad; and means for forcing the additional logic to a predefined state; in which said input multiplexer and said output multiplexer have control inputs that are responsive to a control signal having a normal state or a test state; when said control signal has said normal state, said input multiplexer is controlled to connect said first output of said additional logic to said input of said microprocessor, and said output multiplexer is controlled to connect said second output of said additional logic to said output pad; and when said control signal has said test state, said input multiplexer is controlled to connect said input pad to said input of said microprocessor, said output multiplexer is controlled to connect said output of said microprocessor to said output pad and said means forces said additional logic to said predefined state.
Claim 4
Dependent Claim
255 words
An integrated circuit comprising: a die having an input pad and an output pad; a macrofunctional unit that is formed on the die and has an input and an output; additional logic that is formed on the die and has a first output, a second output, a first input that is connected to the input pad and a second input that is connected to said output of the macrofunctional unit; an input switch for selectively connecting the input pad or said first output of the additional logic to said input of the macrofunctional unit; an output switch for selectively connecting said output of the macrofunctional unit or said second output of the additional logic to the output pad; and means for forcing the additional logic to a predefined state; in which said input multiplexer and said output multiplexer have control inputs that are responsive to a control signal having a normal state or a test state; when said control signal has said normal state, said input multiplexer is controlled to connect said first output of said additional logic to said input of said microprocessor, and said output multiplexer is controlled to connect said second output of said additional logic to said output pad; and when said control signal has said test state, said input multiplexer is controlled to connect said input pad to said input of said microprocessor, said output multiplexer is controlled to connect said output of said microprocessor to said output pad and said means forces said additional logic to said predefined state.
Claim 5
Dependent Claim
15 words
An integrated circuit as defined in claim 2 wherein the macrofunctional unit comprises a microprocessor.
Claim 6
Dependent Claim
24 words
An integrated circuit as defined in claim 2 wherein the input switch includes an input multiplexer and the output switch includes an output multiplexer.
Claim 7
Dependent Claim
23 words
An integrated circuit as defined in claim 2 in which the macrofunctional unit comprises a microprocessor that is embedded in the additional logic.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-11-20 | 1999-05-22 | 1999-11-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-11-20 | 2003-05-22 | 2003-11-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-11-20 | 2007-05-22 | 2007-11-21 | $7700.00 | Window Closed / Lapsed |