Address handler for an asynchronous transfer mode switch

Claim 2

In an address handling circuit for an asynchronous transfer mode switch which processes a cell data stream including a plurality of cells having a header portion with a virtual channel identifier (VCI) and a virtual path identifier (VPI) and having a data payload portion, an improved address handling circuit comprising: temporary storage means for temporarily storing at least one current cell for address processing; virtual channel (VC) filter means, coupled to said temporary storage means and including VC address storage means for storing at least one selected VCI, corresponding VC matching data and a corresponding cell identifier, said VC filter means for comparing data from said header portion of said at least one current cell with said at least one selected VCI to identify cells matching said at least one selected VCI and including VC matching means, coupled to said VC filter means, for indicating a match; virtual path (VP) filter means, connected to said temporary storage means and including VP address storage means for storing at least one selected VPI, corresponding VP matching data and a corresponding cell identifier, said VP filter means for comparing said data from said header portion of said at least one current cell with said at least one selected VPI to identify cells matching said at least one selected VPI and including VP matching means, coupled to said VP filter means, for indicating a match, wherein said VP filter means has lower priority than said VC filter means; and match priority means, coupled to said VC matching means of said VC filter means and said VP matching means of said VP filter means, for retrieving said matching data from a highest priority filter means having a match.

Claim 3

The improved address handling circuit of claim 1 wherein said matching data includes an address storage portion identifying an address in one of said VC address storing means and said VP address storing means and wherein said cell identifier contains routing data.

Claim 4

The improved address handling circuit of claim 1 wherein said VC filter means stores at least one selected VPI/VCI.

Claim 5

The improved address handling circuit of claim 2 further comprising: control means connected to said match priority means for retrieving said corresponding cell identifier from one of said VC address storage means and said VP address storage means identified by said address storage portion.

Claim 6

The improved address handling circuit of claim 4 wherein said cell identifier includes routing data for said current cell.

Claim 7

The improved address handling circuit of claim 4 further comprising: combining means, coupled to said control means, for combining said cell identifier with said current cell.

Claim 8

The improved address handling circuit of claim 6 wherein said combining means stores said cell identifier in said header portion.

Claim 9

The improved address handling circuit of claim 6 wherein said combining means appends said cell identifier at a front end of said current cell.

Claim 10

The improved address handling circuit of claim 6 wherein said combining means appends said cell identifier at a rear end of said current cell.

Claim 11

The improved address handling circuit of claim 1 further comprising: first sub-VP filter means, coupled to said temporary storage means and including first sub-VP address storage means for storing at least one selected first sub-VPI, corresponding first sub-VPI matching data and a corresponding cell identifier, for comparing data from said header portion of said at least one current cell with said at least one selected first sub-VPI to identify cells matching said at least one selected first sub-VPI and including first sub-VPI matching means, coupled to said first sub-VP filter means, for indicating a match.

Claim 12

The improved address handling circuit of claim 10 wherein said first sub-VPI utilizes a plurality of bits of said VCI.

Claim 13

The improved address handling circuit of claim 11 wherein said first sub-VPI utilizes 12 bits of a 16 bit VCI.

Claim 14

The improved address handling circuit of claim 10 wherein said first sub-VP filter means has higher priority than said VP filter means and lower priority than said VC filter means.

Claim 15

The improved address handling circuit of claim 10 further comprising: second sub-VP filter means, coupled to said temporary storage means and including second sub-VP address storage means for storing at least one selected second sub-VPI, corresponding second sub-VPI matching data and a corresponding cell identifier, for comparing data from said header portion of said at least one current cell with said at least one selected second sub-VPI to identify cells matching said at least one selected second sub-VPI and including second sub-VPI matching means, coupled to said second sub-VP filter means, for indicating a match.

Claim 16

The improved address handling circuit of claim 14 wherein said second sub-VPI utilizes a plurality of bits of said VCI.

Claim 17

The improved address handling circuit of claim 14 wherein said second sub-VPI utilizes 8 bits of a 16 bit VCI.

Claim 18

The improved address handling circuit of claim 14 wherein said second sub-VP filter means has higher priority than said VP filter means and lower priority than said first sub-VP filter means.

Claim 19

The improved address handling circuit of claim 14 further comprising: third sub-VP filter means, coupled to said temporary storage means and including third sub-VP address storage means for storing at least one selected third sub-VPI, corresponding third sub-VPI matching data and a corresponding cell identifier, for comparing data from said header portion of said at least one current cell with said at least one selected third sub-VPI to identify cells matching said at least one selected third sub-VPI and including third sub-VPI matching means, coupled to said third sub-VP filter means, for indicating a match.

Claim 20

The improved address handling circuit of claim 18 wherein said third sub-VPI utilizes a plurality of bits of said VCI.

Claim 21

The improved address handling circuit of claim 18 wherein said third sub-VPI utilizes 8 bits of a 16 bit VCI.

Claim 22

The improved address handling circuit of claim 18 wherein said third sub-VP filter means has higher priority than said VP filter means and lower priority than said second sub-VP filter means.

Claim 23

The improved address handling circuit of claim 18 further comprising: fourth sub-VP filter means, coupled to said temporary storage means and including fourth sub-VP address storage means for storing at least one selected fourth sub-VPI, corresponding fourth sub-VPI matching data and a corresponding cell identifier, for comparing data from said header portion of said at least one current cell with said at least one selected fourth sub-VPI to identify cells matching said at least one selected fourth sub-VPI and including fourth sub-VPI matching means, coupled to said fourth sub-VP filter means, for indicating a match.

Claim 24

The improved address handling circuit of claim 22 wherein said fourth sub-VPI utilizes a plurality of bits of said VCI.

Claim 25

The improved address handling circuit of claim 22 wherein said fourth sub-VPI utilizes 8 bits of a 16 bit VCI.

Claim 26

The improved address handling circuit of claim 22 wherein said fourth sub-VP filter means has higher priority than said VP filter means and lower priority than said third sub-VP filter means.

Claim 27

The improved address handling circuit of claim 22 wherein said temporary storage means includes a temporary cell buffer for storing at least one current cell; and a header register for storing data from said header portion of said at least one current cell.

Claim 28

The improved address handling circuit of claim 26 wherein said filter means include a comparand register for storing data from said header portion and said improved address handling circuit further includes comparison control means for loading said data from said header portion stored in said header register into said comparand register.

Claim 29

The improved address handling circuit of claim 22 wherein at least one of said VP filter means and said VC filter means includes a content addressable memory (CAM).

Claim 30

The improved address handling circuit of claim 28 further comprising: processor interfacing means for interfacing said CAMs with an external processor, wherein said external processor provides configuration data, said corresponding matching data, said cell identifier, and at least one of said selected VPI, said selected VCI, said first selected sub-VPI, said second selected sub-VPI, said third selected sub-VPI, and said fourth selected sub-VPI.

Claim 31

The improved address handling circuit of claim 24 wherein at least one of said VC filter means and said VP filter means includes masking means for masking out portions of said header to allow matches on a remaining portion of said header.

Claim 32

The improved address handling circuit of claim 1 wherein said cells are fixed-length.

Claim 33

In an address handling circuit for an asynchronous transfer mode switch which processes a cell data stream including a plurality of cells having a header portion with a virtual channel identifier (VCI) and a virtual path identifier (VPI) and having a data payload portion, an improved address handling circuit comprising: virtual channel (VC) cell routing means, connected to an ATM switch fabric, for routing cells transferred to an input thereof to said ATM switch fabric; VC filter means, connected in said cell data stream, having a first output connected to said VC cell routing means and including a VC address storage means for storing at least one VPI/VCI, for filtering said cell data stream provided at a first input thereof to identify cells having said at least one VPI/VCI, for transferring said cells with said at least one VPI/VCI to said VC cell routing means and for transferring cells which do not have said at least one VPI/VCI to a second output thereof; virtual path (VP) cell routing means for routing cells transferred to an input thereof to said ATM switch fabric; VP filter means, connected in said cell data stream, having a first output connected to said VP cell routing means and including a VP address storage means for storing at least one VPI, for filtering said cell data stream provided at a first input thereof to identify cells having said at least one VPI, for transferring said cells with said at least one VPI to said VP routing means and for transferring cells which do not have said at least one VPI to a second output thereof; first sub-VP cell routing means, connected to an ATM switch fabric, for routing cells input thereto to said ATM switch fabric; and first sub-VP filter means, having a first input connected to said second output of said VC filter means and a first output connected to said first sub-VP cell routing means, and including first sub-VP address storage means for storing at least one first sub-VP identifier (sub-VPI), for filtering cells having said at least one first sub-VPI, for transferring said cells with said at least one first sub-vP identifier to said first sub-VP cell routing means and for transferring cells which do not have said at least one first sub-VPI to a second output thereof.

Claim 34

In an address handling circuit for an asynchronous transfer mode switch which processes a cell data stream including a plurality of cells having a header portion with a virtual channel identifier (VCI) and a virtual path identifier (VPI) and having a data payload portion, an improved address handling circuit comprising: virtual channel (VC) cell routing means, connected to an ATM switch fabric, for routing cells transferred to an input thereof to said ATM switch fabric; VC filter means, connected in said cell data stream, having a first output connected to said VC cell routing means and including a VC address storage means for storing at least one VPI/VCI, for filtering said cell data stream provided at a first input thereof to identify cells having said at least one VPI/VCI, for transferring said cells with said at least one VPI/VCI to said VC cell routing means and for transferring cells which do not have said at least one VPI/VCI to a second output thereof; virtual path (VP) cell routing means for routing cells transferred to an input thereof to said ATM switch fabric; VP filter means, connected in said cell data stream, having a first output connected to said VP cell routing means and including a VP address storage means for storing at least one VPI, for filtering said cell data stream provided at a first input thereof to identify cells having said at least one VPI, for transferring said cells with said at least one VPI to said VP routing means and for transferring cells which do not have said at least one VPI to a second output thereof; first sub-VP cell routing means, connected to an ATM switch fabric, for routing cells input thereto to said ATM switch fabric; and first sub-VP filter means, having a first input connected to said second output of said VC filter means and a first output connected to said first sub-VP cell routing means, and including first sub-VP address storage means for storing at least one first sub-VP identifier (sub-VPI), for filtering cells having said at least one first sub-VPI, for transferring said cells with said at least one first sub-vP identifier to said first sub-VP cell routing means and for transferring cells which do not have said at least one first sub-VPI to a second output thereof.

Claim 35

The improved address handling circuit of claim 32 wherein said cells are fixed-length.

Claim 36

The improved address handling circuit of claim 32 further comprising: an input interface; and idle cell filter means, having an input connected to said input interface, for removing idle cells, inserted in said data stream to maintain synchronization, from said cell data stream, wherein non-idle cells are output to said VC filter means.

Claim 37

The improved address handling circuit of claim 32 wherein an input of said VP filter means is connected to said second output of said VC filter means.

Claim 38

The improved address handling circuit of claim 32 wherein said first sub-VPI utilizes 12 bits of a 16 bit VCI.

Claim 39

The improved address handling circuit of claim 32 further comprising: second sub-VP cell routing means, connected to an ATM switch fabric, for routing cells input thereto to said ATM switch fabric; and second sub-VP filter means, having a first input connected to said second output of said first sub-VP filter means and a first output connected to said second sub-VP cell routing means, and including second sub-VP address storage means for storing at least one second sub-VPI, for filtering cells having said at least one second sub-VPI, for transferring said cells with said at least one second sub-VP identifier to said second sub-VP cell routing means and for transferring cells which do not have said at least one second sub-VPI to a second output thereof.

Claim 40

The improved address handling circuit of claim 37 wherein said second sub-VPI utilizes 8 bits of a 16 bit VCI.

Claim 41

The improved address handling circuit of claim 37 further comprising: third sub-VP cell routing means, connected to an ATM switch fabric, for routing cells input thereto to said ATM switch fabric; and third sub-VP filter means, having a first input connected to said second output of said first sub-VP filter means and a first output connected to said third sub-VP cell routing means, and including a third sub-VP address storage means for storing at least one third sub-VPI, for filtering cells having said at least one third sub-VPI, for transferring said cells with said at least one third sub-VPI to said third sub-VP cell routing means and for transferring cells which do not have said at least one third sub-VPI to a second output thereof.

Claim 42

The improved address handling circuit of claim 39 wherein said third sub-VPI utilizes 6 bits of a 16 bit VCI.

Claim 43

The improved address handling circuit of claim 39 further comprising: fourth sub-VP cell routing means, connected to an ATM switch fabric, for routing cells input thereto to said ATM switch fabric; and fourth sub-VP filter means, having a first input connected to said second output of said first sub-VP filter means and a first output connected to said fourth sub-VP cell routing means, and including fourth sub-VP address storage means for storing at least one fourth sub-VPI, for filtering cells having said at least one fourth sub-VPI, for transferring said cells with said at least one fourth sub-VPI to said fourth sub-VP cell routing means and for transferring cells which do not have said at least one fourth sub-VPI to a second output thereof.

Claim 44

The improved address handling circuit of claim 41 wherein said fourth sub-VPI utilizes 4 bits of a 16 bit VCI.

Claim 45

The improved address handling circuit of claim 41 wherein said second output of said fourth sub-VP filter is connected to said first input of said VP filter means.

Claim 46

The cell filter of claim 32 further comprising: a cell error processing circuit connected to said second output of said VP filter means.