Patent US5467306A successfully refreshed from Google Patents.
US5467306A
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Method of using source bias to increase threshold voltages and/or to correct for over-erasure of flash eproms
Assignee: Texas Instruments Inc
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Filing: 1993-10-04
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Granted: 1995-11-14
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Expires: 2013-10-04
Abstract
Abstract The method of this invention allows use of a smaller wordline voltage Vp1 during programming. In addition, the method results in a relatively narrow distribution of threshold voltages Vt when used to flash program an array of memory cells (10). The method of this invention increases compaction gate-current efficiency by reverse biasing the source (11)/substrate (23) junction of the cell being programmed. The reverse biasing is accomplished, for example, by applying a bias voltage to the source (11 ) or by placing a diode (27), a resistor (29) or other impedance in series with the source (11). The reverse biasing limits the source current (Is) of cell being programmed and of the entire array during flash-programming compaction.
Inventors
- 👤 Cetin Kaya
- 👤 Wayland B. Holland
- 👤 Rabah Mezenner
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 16:37
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/10; G11C16/12
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
137 words
A method for increasing the threshold voltage of at least one of a plurality of floating-gate memory cells in a nonvolatile integrated-circuit memory having a substrate connected to a reference voltage each said memory cells being of the single-transistor, non-split-gate type, said method comprising: causing the voltage on the control gates of said plurality of memory cells to have a positive value with respect to said reference voltage; causing the voltage on the sources of said plurality of memory cells to have a positive value with respect to said reference voltage; and causing a current to flow into the drains of said plurality of memory cells; said voltage on the control gates having a value less than the typical threshold voltage of said plurality of cells with said voltage on said sources of said plurality of cells.
Claim 2
Independent Claim
137 words
A method for increasing the threshold voltage of at least one of a plurality of floating-gate memory cells in a nonvolatile integrated-circuit memory having a substrate connected to a reference voltage each said memory cells being of the single-transistor, non-split-gate type, said method comprising: causing the voltage on the control gates of said plurality of memory cells to have a positive value with respect to said reference voltage; causing the voltage on the sources of said plurality of memory cells to have a positive value with respect to said reference voltage; and causing a current to flow into the drains of said plurality of memory cells; said voltage on the control gates having a value less than the typical threshold voltage of said plurality of cells with said voltage on said sources of said plurality of cells.
Claim 3
Dependent Claim
28 words
The method of claim 1, wherein said positive voltage on said sources is caused by connecting at least one diode transistor between said sources and said reference voltage.
Claim 4
Dependent Claim
26 words
The method of claim 1, wherein said positive voltage on said sources is connected by a feedback amplifier to said control gate of said memory cell.
Claim 5
Dependent Claim
20 words
The method of claim 1, wherein said voltage on said control gates is adjusted to cause optimum gate current efficiency.
Claim 6
Dependent Claim
14 words
The method of claim 1, wherein said voltage on said control gates is ramped.
Claim 7
Dependent Claim
29 words
The method of claim 1, wherein said positive voltage on said sources is caused by a current flowing through a resistor connected between said sources and said reference voltage.
Claim 8
Dependent Claim
17 words
The method of claim 1, wherein said plurality of memory cells is a column of memory cells.
Claim 9
Dependent Claim
17 words
The method of claim 1, wherein said plurality of memory cells is a row of memory cells.
Claim 10
Dependent Claim
20 words
The method of claim 1, wherein said plurality of memory cells is all of said memory cells in said memory.
Claim 11
Dependent Claim
68 words
The method of claim 1, wherein each of said plurality of memory cells is connected in parallel, wherein said voltage on said sources is caused to have a positive value by causing current to flow from said sources, and wherein said current is caused to flow into said drains of said memory cells by a voltage source connected to said drains, all for a period of one second.
Claim 12
Dependent Claim
20 words
The method of claim 1, said memory further having a ground voltage, wherein said reference voltage is said ground voltage.
Claim 13
Independent Claim
134 words
A method for increasing the threshold voltage of at least one of a plurality of floating-gate memory cells in a nonvolatile integrated-circuit memory having a substrate, each said memory cell being of the single-transistor, non-split-gate type, said method comprising: causing the voltage on the control gates of said memory cells to have a positive value with respect to the voltage on said substrate; reverse-biasing the sources of said memory cells with respect to said substrate; reverse biasing the drains of said memory cells with respect to said substrate; and allowing a current to flow between said drains and said sources of at least some of said plurality of cells; said voltage on the control gates having a value less than the typical threshold voltage of said plurality of memory cells with said sources reverse-biased.
Claim 14
Independent Claim
134 words
A method for increasing the threshold voltage of at least one of a plurality of floating-gate memory cells in a nonvolatile integrated-circuit memory having a substrate, each said memory cell being of the single-transistor, non-split-gate type, said method comprising: causing the voltage on the control gates of said memory cells to have a positive value with respect to the voltage on said substrate; reverse-biasing the sources of said memory cells with respect to said substrate; reverse biasing the drains of said memory cells with respect to said substrate; and allowing a current to flow between said drains and said sources of at least some of said plurality of cells; said voltage on the control gates having a value less than the typical threshold voltage of said plurality of memory cells with said sources reverse-biased.
Claim 15
Dependent Claim
25 words
The method of claim 12, wherein said sources are reverse-biased with respect to said substrate by a transistor diode connected in series with said sources.
Claim 16
Dependent Claim
25 words
The method of claim 12, wherein the voltage on said sources is connected by a feedback amplifier to said control gates of said memory cells.
Claim 17
Dependent Claim
29 words
The method of claim 12, wherein said sources are reverse-biased with respect to said substrate by a current flowing through a resistor connected between said sources and said substrate.
Claim 18
Dependent Claim
18 words
The method of claim 12, wherein said plurality of memory cells is a column of said memory cells.
Claim 19
Dependent Claim
18 words
The method of claim 12, wherein said plurality of memory cells is a row of said memory cells.
Claim 20
Dependent Claim
20 words
The method of claim 12, wherein said plurality of memory cells is all of said memory cells in said memory.
Claim 21
Dependent Claim
14 words
The method of claim 12, wherein said voltage on said control gates is ramped.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-11-13 | 1999-05-15 | 1999-11-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-11-13 | 2003-05-15 | 2003-11-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-11-13 | 2007-05-15 | 2007-11-14 | $7700.00 | Window Closed / Lapsed |