US5465346A
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US
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Method and apparatus for synchronous bus interface optimization
Assignee: Dell USA LP
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Filing: 1993-08-05
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Granted: 1995-11-07
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Expires: 2013-08-05
Abstract
Abstract A method and apparatus which enables devices connected to a bus to detect and take advantage of the early arrival of bus signal inputs. A signal arrival encoder circuit included in a device encodes the arrival time of a signal input whose early arrival is desired to be detected. The arrival time of the signal at issue is categorized according to a desired degree of precision or granularity depending upon the complexity of the encoder used in the respective embodiment. The encoded signal arrival information is then used by the respective device to determine when to sample the other respective input signal. By detecting the early arrival of this input, the device is not required to wait for the worst case signal arrival time to utilize the information. This considerably increases system performance.
Inventors
- 👤 Terry J. Parks
- 👤 Darius D. Gaskins
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 21:10
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/13; H03K5/135; H03K2005/00013; H03K2005/00078; H03K2005/00097; H03K2005/00104
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
190 words
A method for reducing the amount of time required for bus cycles in a computer system having a bus, a first device coupled to the bus which generates a signal, and a second device coupled to the bus which receives the signal as an input, wherein the second device includes a signal arrival encoder which encodes the arrival time of the signal, the method comprising the steps of: the first device generating a signal on the bus to the second device on a first bus cycle; the signal arrival encoder monitoring the arrival time of the signal to the second device on said first bus cycle; the signal arrival encoder encoding said arrival time of the signal into signal arrival information; the first device generating the signal on the bus to the second device in a subsequent bus cycle, wherein said subsequent bus cycle occurs after said first bus cycle and after said steps of monitoring and encoding; the second device latching the signal during said subsequent bus cycle, wherein the second device uses said signal arrival information in determining when to latch the signal during said subsequent bus cycle.
Claim 2
Independent Claim
190 words
A method for reducing the amount of time required for bus cycles in a computer system having a bus, a first device coupled to the bus which generates a signal, and a second device coupled to the bus which receives the signal as an input, wherein the second device includes a signal arrival encoder which encodes the arrival time of the signal, the method comprising the steps of: the first device generating a signal on the bus to the second device on a first bus cycle; the signal arrival encoder monitoring the arrival time of the signal to the second device on said first bus cycle; the signal arrival encoder encoding said arrival time of the signal into signal arrival information; the first device generating the signal on the bus to the second device in a subsequent bus cycle, wherein said subsequent bus cycle occurs after said first bus cycle and after said steps of monitoring and encoding; the second device latching the signal during said subsequent bus cycle, wherein the second device uses said signal arrival information in determining when to latch the signal during said subsequent bus cycle.
Claim 3
Dependent Claim
36 words
The method of claim 1, wherein the bus operates according to a clocking signal and wherein the signal arrival encoder monitors the arrival time of the signal to the second device relative to said clocking signal.
Claim 4
Dependent Claim
92 words
The method of claim 2, wherein said step of the signal arrival encoder monitoring the arrival time of the signal to the second device on said first bus cycle comprises determining if the signal arrives before or after an edge of said clocking signal; wherein said step of the signal arrival encoder encoding said arrival time of the signal into signal arrival information comprises encoding said arrival time of the signal into one or more bits indicating an early or late signal arrival time relative to said edge of said clocking signal.
Claim 5
Dependent Claim
112 words
The method of claim 3, wherein said signal arrival information comprises one or more bits indicating an early or late signal arrival time; wherein said step of the second device latching the signal during said subsequent bus cycle using said signal arrival information further comprises: the second device latching in the signal on a first edge of said clocking signal in said first bus cycle if said one or more bits indicate an early arrival time; and the second device latching in the signal on a second edge of said clocking signal after said first edge in said first bus cycle if said one or more bits indicate a late arrival time.
Claim 6
Dependent Claim
20 words
The method of claim 1, wherein said subsequent bus cycle is the next cycle immediately after said first bus cycle.
Claim 7
Dependent Claim
157 words
A computer system including a signal arrival encoder which encodes the arrival time of one or more signals on a bus to reduce the amount of time required for bus cycles in the computer system, the computer system comprising: a bus; a first device coupled to the bus which generates a signal; and a second device coupled to the bus which receives said signal as an input and latches said signal from the bus, wherein the second device includes: a signal arrival encoder including an input coupled to said bus which receives said signal from said first device, where said signal arrival encoder comprises: means for monitoring the arrival time of the signal to the second device on a first bus cycle; and means for encoding said arrival time of the signal into signal arrival information; wherein the second device uses said signal arrival information in determining when to latch in the signal from said first device.
Claim 8
Dependent Claim
157 words
A computer system including a signal arrival encoder which encodes the arrival time of one or more signals on a bus to reduce the amount of time required for bus cycles in the computer system, the computer system comprising: a bus; a first device coupled to the bus which generates a signal; and a second device coupled to the bus which receives said signal as an input and latches said signal from the bus, wherein the second device includes: a signal arrival encoder including an input coupled to said bus which receives said signal from said first device, where said signal arrival encoder comprises: means for monitoring the arrival time of the signal to the second device on a first bus cycle; and means for encoding said arrival time of the signal into signal arrival information; wherein the second device uses said signal arrival information in determining when to latch in the signal from said first device.
Claim 9
Dependent Claim
51 words
The computer system of claim 6, wherein the bus operates according to a clocking signal; and wherein the signal arrival encoder includes an input receiving said bus clocking signal, and wherein the signal arrival encoder monitors the arrival time of the signal to the second device relative to said clocking signal.
Claim 10
Dependent Claim
77 words
The method of claim 7, wherein said means for monitoring the arrival time of the signal to the second device determines if the signal arrives before or after an edge of said clocking signal; wherein said means for encoding said arrival time of the signal into signal arrival information encodes said arrival time of the signal into one or more bits indicating an early or late signal arrival time relative to said edge of said clocking signal.
Claim 11
Dependent Claim
83 words
The computer system of claim 8, wherein said signal arrival information comprises one or more bits indicating an early or late signal arrival time; wherein the second device latches in the signal on a first edge of said clocking signal if said one or more bits indicate an early arrival time; and wherein the second device latches in the signal on a second edge of said clocking signal after said first edge if said one or more bits indicate a late arrival time.
Claim 12
Dependent Claim
33 words
The computer system of claim 6, wherein the second device uses said signal arrival information in said first bus cycle in determining when to latch in the signal in said first bus cycle.
Claim 13
Dependent Claim
38 words
The computer system of claim 6, wherein the second device uses said signal arrival information in a subsequent bus cycle after said first bus cycle in determining when to latch in the signal in said subsequent bus cycle.
Claim 14
Dependent Claim
93 words
The computer system of claim 11, wherein said signal arrival information comprises one or more bits indicating an early or late signal arrival time; wherein the second device latches in the signal on a first edge of said clocking signal in said subsequent bus cycle if said one or more bits indicate an early arrival time; and wherein the second device latches in the signal on a second edge of said clocking signal after said first edge in said subsequent bus cycle if said one or more bits indicate a late arrival time.
Claim 15
Dependent Claim
20 words
The computer system of claim 12, wherein said subsequent cycle is the next cycle immediately after said first bus cycle.
Claim 16
Independent Claim
143 words
A method for reducing the amount of time required for bus cycles in a computer system having a bus, a first device coupled to the bus which generates a signal, and a second device coupled to the bus which receives the signal as an input, wherein the second device includes a signal arrival encoder which encodes the arrival time of the signal, the method comprising the steps of: the first device generating a signal on the bus to the second device on a first bus cycle; the signal arrival encoder monitoring the arrival time of the signal to the second device on said first bus cycle; the signal arrival encoder encoding said arrival time of the signal into signal arrival information; the second device latching the signal, wherein the second device uses said signal arrival information in determining when to latch the signal.
Claim 17
Independent Claim
143 words
A method for reducing the amount of time required for bus cycles in a computer system having a bus, a first device coupled to the bus which generates a signal, and a second device coupled to the bus which receives the signal as an input, wherein the second device includes a signal arrival encoder which encodes the arrival time of the signal, the method comprising the steps of: the first device generating a signal on the bus to the second device on a first bus cycle; the signal arrival encoder monitoring the arrival time of the signal to the second device on said first bus cycle; the signal arrival encoder encoding said arrival time of the signal into signal arrival information; the second device latching the signal, wherein the second device uses said signal arrival information in determining when to latch the signal.
Claim 18
Dependent Claim
21 words
The method of claim 14, wherein said step of the second device latching the signal occurs during said first bus cycle.
Claim 19
Dependent Claim
79 words
The method of claim 14, further comprising the step of: the first device generating the signal on the bus to the second device in a subsequent bus cycle, wherein said subsequent bus cycle occurs after said first bus cycle and after said steps of monitoring and encoding; wherein said step of the second device latching the signal occurs on said subsequent bus cycle, wherein the second device uses said signal arrival information in determining when to latch the signal.
Claim 20
Dependent Claim
36 words
The method of claim 14, wherein the bus operates according to a clocking signal and wherein the signal arrival encoder monitors the arrival time of the signal to the second device relative to said clocking signal.
Claim 21
Dependent Claim
92 words
The method of claim 14, wherein said step of the signal arrival encoder monitoring the arrival time of the signal to the second device on said first bus cycle comprises determining if the signal arrives before or after an edge of said clocking signal; wherein said step of the signal arrival encoder encoding said arrival time of the signal into signal arrival information comprises encoding said arrival time of the signal into one or more bits indicating an early or late signal arrival time relative to said edge of said clocking signal.
Claim 22
Dependent Claim
112 words
The method of claim 18, wherein said signal arrival information comprises one or more bits indicating an early or late signal arrival time; wherein said step of the second device latching the signal during said subsequent bus cycle using said signal arrival information further comprises: the second device latching in the signal on a first edge of said clocking signal in said first bus cycle if said one or more bits indicate an early arrival time; and the second device latching in the signal on a second edge of said clocking signal after said first edge in said first bus cycle if said one or more bits indicate a late arrival time.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-11-06 | 1999-05-08 | 1999-11-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-11-06 | 2003-05-08 | 2003-11-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-11-06 | 2007-05-08 | 2007-11-07 | $7700.00 | Window Closed / Lapsed |