Semiconductor memory device having shifting circuit connected between data bus lines and data buffer circuits for changing connections therebetween

Claim 2

A semiconductor memory device comprising: a) a memory cell array divided into a plurality of memory cell sub-arrays each implemented by a plurality of addressable memory cells for storing internal data bits, respectively; b) a plurality of data buffer circuits operative to change data bits between said internal data bits and external data bits, and having respective priorities different from one another; c) an addressing means operative to couple selected addressable memory cells respectively selected from said plurality of memory cell sub-arrays to said plurality of data buffer circuits; and d) a shifting circuit coupled between said addressing means and said plurality of data buffer circuits, and operative to respectively connect said plurality of memory cell sub-arrays to said data buffer circuits when a defective memory cell sub-array with a defective memory cell is not incorporated in said plurality of memory cell sub-arrays, said shifting circuit being further operative to connect available memory cell sub-arrays without said defective memory cell to the data buffer circuits in an order of said priority and to isolate said defective memory cell sub-array or sub-arrays from the data buffer circuit or circuits lower in said priority.

Claim 3

The semiconductor memory device as set forth in claim 1, in which said plurality of addressable memory cells of each memory cell sub-array are broken down into regular addressable memory cells and redundant addressable memory cells with which said defective memory cell or cells contained in said regular addressable memory cells are replaced.

Claim 4

The semiconductor memory device as set forth in claim 1, in which said plurality of addressable memory cells of each memory cell sub-array are broken down into regular addressable memory cells and redundant addressable memory cells with which said defective memory cell or cells contained in said regular addressable memory cells are replaced, and in which said addressing means comprises a plurality of sets of regular and redundant data propagation paths respectively associated with said plurality of memory cell sub-arrays, the regular and redundant data propagation paths of each of said plurality of sets being selectively coupled to said regular addressable memory cells and said redundant addressable memory cells for supplying data bits therefrom and thereto, a plurality of sets of regular and redundant word lines respectively associated with said plurality of memory cell sub-arrays, the regular and redundant word lines of each of said plurality of sets being selectively coupled to said regular addressable memory cells and said redundant addressable memory cells and operative to connect the associated regular addressable memory cells or said redundant addressable memory cells to said plurality of regular and redundant data propagation paths when said regular and redundant word lines are selectively activated, a row selecting system responsive to first address signals for energizing one of said regular and redundant word lines of each of said plurality of sets of regular and redundant word lines, and a column selecting system responsive to second address signals for coupling regular and redundant data propagation paths respectively selected from said plurality of sets of regular and redundant data propagation paths to said plurality of data buffer circuits.

Claim 5

The semiconductor memory device as set forth in claim 1, in which said shifting circuit comprises a gate control circuit producing gate control signals indicative of existence of said defective memory cell sub-array or sub-arrays, an isolating circuit coupled between said data buffer circuit or circuits lower in said priority and a source of constant voltage for supplying the constant voltage to said data buffer circuit or circuits lower in said priority when said defective memory cell sub-array or sub-arrays exist, said isolating circuit coupling said data buffer circuit or circuits lower in said priority through said addressing means to one or ones of said plurality of memory cell sub-arrays when said defective memory cell sub-array is not incorporated in said plurality of memory cell sub-arrays, and a switching unit coupled between said addressing means and said data buffer circuits and operative to couple the others of said plurality of memory cell sub-arrays to the data buffer circuits higher in said priority when said defective memory cell sub-array is not incorporated in said plurality of memory cell sub-arrays, said switching unit being further operative to couple said available memory cell sub-arrays to said data buffer circuits higher in said priority when said defective memory cell sub-array or arrays are incorporated in said plurality of memory cell sub-arrays.

Claim 6

The semiconductor memory device as set forth in claim 4, in which said switching unit comprises a plurality of first blowable fuse elements for electrically connecting said plurality of memory cell sub-arrays except for the plurality of memory cell sub-array or sub-arrays coupled to the data buffer circuit or circuits lower in said priority to said plurality of data buffer circuits higher in said priority, respectively, and a plurality of second blowable fuse elements respectively paired with said plurality of first blowable fuse elements for forming a plurality of blowable fuse pairs, and connecting said others of said plurality of memory cell sub-arrays to said data buffer circuits higher in said priority, said plurality of second blowable fuse elements being broken when said defective memory cell sub-array is not incorporated in said plurality of memory cell sub-arrays, either first or second blowable fuse element of each blowable fuse pair being broken depending upon the location of said defective memory cell sub-array or sub-arrays in said plurality of memory cell sub-arrays.

Claim 7

The semiconductor memory device as set forth in claim 4, in which said switching unit comprises a plurality of first transfer gates operative to electrically connect said plurality of memory cell sub-arrays except for the memory cell sub-array or sub-arrays coupled to the data buffer circuit or circuits lower in said priority to said plurality of data buffer circuits, respectively, and a plurality of second transfer gates respectively paired with said plurality of first transfer gates for forming a plurality of transfer gate pairs, and operative to connect said others of said plurality of memory cell sub-arrays to said data buffer circuits higher in said priority, said plurality of first transfer gates and said plurality of second transfer gates being turned on and off, respectively, when said defective memory cell sub-array is not incorporated in said plurality of memory cell sub-arrays, either first or second transfer gate of each transfer gate pair being turned on depending upon the location of said defective memory cell sub-array or sub-arrays in said plurality of memory cell sub-arrays.